Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit CharacteristicsMarkkuopin chang[0]hangting lue[0]chihping chen[0]yanru chen[0]yihsuan hsiao[0]chihchang hsieh[0]yenhao shih[0]tahone yang[0]kuangchao chen[0]chunhsiung hung[0]chihyuan lu[0]2012.Cited by: 11|Bibtex|Views17|DOI:https://doi.org/10.1109/IMW.2012.6213641Other Links: academic.microsoft.comKeywords: logic gatethin film transistordecodinglogic gatesthree dimensionalMore(1+)Code: Data: Full Text (Upload PDF)PPT (Upload PPT)SimilarReferenceCitedUpload PPTYour rating :0 TagsCommentsSubmit
