A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference

As well as low jitter performance, modern wireless communication standards also require low-spurious PLLs, since spurs cause the violation of emission masks and worse inter-carrier interference (ICI) in OFDM systems like 5G. Cascaded PLLs have been recently exploited for low-jitter frequency synthesis with a large frequency multiplication ratio N [1]. Previous fractional cascaded PLLs use a 1 ^st -stage fractional-N PLL and a 2 ^nd -stage integer-N PLL [2] or a 1 ^st stage integer-N PLL and a 2 ^nd -stage fractional-N PLL [3]. Similar to single-stage PLLs, fractional spurs are degraded at near-integer channels in the conventional cascaded PLLs since those spurs appear at too low offset frequencies to be filtered by PLL loop function. To meet the ever-growing demand on low spur levels, the fractional spurs in cascaded PLLs must be suppressed.