Yuncheng ZHANG - Tokyo Inst Technol, Dept Elect & Elect Engn, Meguro Ku, 2-12-1-S3-27 Ookayama, Tokyo 1528552, Japan

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Yuncheng ZHANG currently works at the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology. Yuncheng does research in Electronic Engineering.

Research Interests

Papers共 42 篇Author StatisticsCo-AuthorSimilar Experts

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A 28ghz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond

Yi Zhang,Minzhe Tang,Jian Pang,Zheng Li,Dongfan Xu,Dingxin Xu,Yuncheng Zhang,Kazuaki Kunihiro,Hiroyuki Sakai,Atsushi Shirane,Kenichi Okada

Symposium on VLSI Technologypp.1-2, (2024)

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A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a $-$ 62.1-Dbc Fractional Spur

Dingxin Xu,Zezheng Liu, Yifeng Kuai, Hongye Huang,Yuncheng Zhang,Zheng Sun,Bangan Liu,Wenqian Wang,Yuang Xiong,Junjun Qiu,Waleed Madany,Yi Zhang,Ashbir Aviat Fadila,Atsushi Shirane,Kenichi Okada

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2024)

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A VCO with Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network

Dingxin Xu,Zheng Sun,Yuang Xiong,Yuncheng Zhang,Hongye Huang,Zezheng Liu,Ashbir Aviat Fadila,Atsushi Shirane,Kenichi Okada

IEEE Solid-State Circuits Letters (2024): 171-174

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24.3 A 236-to-266ghz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS

Chun Wang,Hans Herdian, Wenbin Zheng,Chenxin Liu,Jill Mayeda, Yuxuan Liu, Olivia Angel Yong,Wenqian Wang,Yuncheng Zhang,Carrel da Gomez,Abanob Shehata,Sena Kato,Ibrahim Abdo,Teruo Jyo,Hiroshi Hamada,Hiroyuki Takahashi,Hiroyuki Sakai,Atsushi Shirane,Kenichi Okada

2024 IEEE International Solid-State Circuits Conference (ISSCC) (2024): 415-417

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A Fully Synthesizable Fractional-N MDLL with Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range

Hongye Huang,Bangan Liu,Zezheng Liu,Dingxin Xu,Yuncheng Zhang,Waleed Madany,Junjun Qiu,Zheng Sun,Ashbir Aviat Fadila,Jian Pang,Zheng Li,Dongwon You,Atsushi Shirane,Kenichi Okada

IEEE SOLID-STATE CIRCUITS LETTERS（2024）

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10.3 A 7ghz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1Dbc Fractional Spur and 143.7fs Integrated Jitter

Dingxin Xu,Zezheng Liu, Yifeng Kuai,Hongye Huang,Yuncheng Zhang,Zheng Sun,Bangan Liu,Wenqian Wang,Yuang Xiong,Junjun Qiu,Waleed Madany,Yi Zhang,Ashbir Aviat Fadila,Atsushi Shirane,Kenichi Okada

IEEE International Solid-State Circuits Conference（2024）

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A 6.5-to-8-ghz Cascaded Dual-Fractional- $N$ Digital PLL Achieving $-$ 52.79-Dbc Fractional Spur with 50-Mhz Reference

Dingxin Xu,Yuncheng Zhang,Hongye Huang,Zheng Sun,Bangan Liu,Ashbir Aviat Fadila,Junjun Qiu,Zezheng Liu,Wenqian Wang,Yuang Xiong,Waleed Madany,Atsushi Shirane,Kenichi Okada

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2024)

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Digital Phase-Locked Loops: Exploring Different Boundaries

Yuncheng Zhang,Dingxin Xu,Kenichi Okada

IEEE OPEN JOURNAL OF THE SOLID-STATE CIRCUITS SOCIETY (2024): 176-192

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A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-Bit Delta-Sigma Modulator and Transformer Combined FIR FIlter

Yuncheng Zhang,Zheng Sun,Bangan Liu,Junjun Qiu,Dingxin Xu,Yi Zhang,Xi Fu,Dongwon You,Hongye Huang,Waleed Madany,Ashbir Aviat Fadila,Zezheng Liu,Wenqian Wang,Yuang Xiong,Atsushi Shirane,Kenichi Okada

IEEE JOURNAL OF SOLID-STATE CIRCUITSno. 4 (2024): 993-1005

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Design of Synthesizable Digital Phase Locked Loops

Yuncheng Zhang,Kenichi Okada

IPSJ Transactions on System and LSI Design Methodologyno. 0 (2024): 44-54

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