32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth

Low-power internet-of-things (IoT) devices sometimes use two independent crystal oscillators (XOs): a 32.768kHz XO for the real-time clock (RTC) and a tens of MHz XO for low-jitter clock and carrier synthesis. To reduce the number of XOs, 32kHz-reference phase-locked loops (PLLs) [1], [2] have been reported. However, the jitter performance is degraded due to narrow loop bandwidth, e.g., less than 3kHz, limited by the 32kHz reference frequency. To break this limitation, a 2.4GHz fractional-N oversampling PLL (OSPLL) with a 32kHz reference is proposed in this paper. The proposed DAC-and DTC-assisted OSPLL realizes a 200kHz loop bandwidth and 5.79ps rms jitter with 4.97mW power consumption in a 65nm CMOS technology.