Infineon Technologies Austria

In this article, the hybrid dc-dc dual-path step-down topology is analyzed and selected for an automotive application due to its numerous benefits: it enables reduced inductor usage, which can be miniaturized, employs an auto-balanced flying capacitor, imposes limited stress on power switches, and offers, at the same time, a relatively wide conversion range. These features are achieved while maintaining the circuit complexity contained compared to many other competing hybrid topologies. A power loss analysis of the converter is carried out, which is exploited to obtain optimal sizing of the power stage and the inductor, and the chip architecture is described. Finally, the benefits of the topology are demonstrated experimentally through a highly-integrated prototype fabricated in 130nm CMOS technology, capable of converting an input voltage from the range 3.3-4.3V down to an output voltage in the range 0.7-1.2V, at a maximum power of 1.8W. The prototype, operating at a switching frequency of 2.5MHz, achieves a peak efficiency of 89.7% at a load current of 500mA, in a compact solution that features a power density of 1.73W/mm2.

Multi-bit quantization allows Delta-Sigma modulators to achieve low oversampling ratios (OSRs), improved jitter tolerance, and relaxed dynamic requirements of the loop filter, but face nonlinearity challenges in the feedback digital-to-analog converter (DAC), requiring complex calibration techniques. Dual quantization using digital DSM (DDSM) has been proposed to overcome this limitation, but state-of-the art DDSM suffers from limited resolution, stability concerns, and digital-analog matching requirements. This work applies a sturdy multistage noise shaping (SMASH) DDSM feedback DAC within a wideband DSM to address these issues. This results in low element mismatch sensitivity, eliminating the need for any DAC calibration. To reduce the effect of dynamic errors in the outer DAC, an inter-symbol-interference (ISI) shuffler is proposed and gain boosting is applied within the DAC elements to address memory effects due to parasitic capacitance. The DSM allows an excess loop-delay (ELD) = 1.5 x T-s in the outermost feedback path to give enough processing time for the SMASH DDSM. The prototype implementation of the 3rd-order continuous-time (CT) DSM shows a 106.2 dB spurious-free dynamic range (SFDR) in an 80 MHz bandwidth without any DAC calibration. Using reference folding and shuffling in the internal Flash quantizer, the DSM is clocked at 2.75 GHz. Implemented in 28 nm CMOS, CT DSM achieves a competitive figure-of-merit (FOM) = 163.7 dB for such extreme linearity.

The efficiency of semiconductor frontend manufacturing highly depends on the optimization of resource allocation. In academic works, scheduling methods, i.e., based on Constraint Programming (CP) or Mixed Integer Programming (MIP), are popular tools for solving this optimization problem. As the problem is NP-hard, complete optimization methods do not scale to the problem size and complexity required for realistic fabwide scheduling. Therefore, the problem is often decomposed and solved locally. While we can track the solution gap or even compute exact solutions for sufficiently small local problem instances, the fab-wide impact of decomposition strategies is yet to be determined in a realistic setting. In this work, we empirically quantify the impact of locally applied optimization on the fab-wide throughput and tardiness. For this evaluation, we use a local CP-based optimization method to compute large-scale schedules in the dynamic and stochastic environment of a semiconductor frontend manufacturing facility. We investigate the local and global impact of our method in different settings using a high-fidelity simulation environment. The results show that the CP-based scheduling method is able to significantly improve locally over advanced expert-drafted heuristics. On the global scale, we show that local optimization delivers inconsistent and varying results, stressing the need for an injection of global information into the local problem formulation.

Semiconductor front-end fabrication facilities (fabs) perform hundreds of manufacturing steps in sequence to produce power electronic devices using specialized equipment such as epitaxy, lithography, and thermal processing tools. Each step is governed by Unit Process Instructions (UPIs) that specify tool configuration parameters, required bill of materials, and operator actions necessary to achieve desired outcomes. Furthermore, UPIs are organized into sequences called process flows that describe all steps required to manufacture advanced semiconductor products. Optimizing UPIs for specific products and tools, and harmonizing UPIs across multiple process flows, is critical for improving yield, reducing energy and material consumption, minimizing waste, achieving sustainable manufacturing practices, and accelerating time-to-market for emerging power electronic applications. The ATRIA project addresses these challenges in gallium nitride (GaN) epitaxy, where UPI optimization is particularly challenging due to the intricate physics governing epitaxial growth and the high dimensionality of the UPI parameter space. To overcome these obstacles, the project aims to: (1) advance digital twin creation by formalizing domain knowledge and the semantics of physics-informed processes, and (2) develop novel optimization and planning methods to refine existing UPIs, design new ones, and harmonize them across process flows. In particular, we aim to research novel hybrid AI approaches that integrate heuristic search methods with physics-informed models based on deep learning and reinforcement learning to enable efficient UPI optimization and harmonization. The proposed methods will be validated using real-world data from an industrial GaN epitaxy tool.

Mechanical Faults in PMSM-driven systems can introduce disturbances and system interruptions leading to reduced performance and reliability. Effective fault diagnosis is essential for early fault detection and identification which enables timely maintenance, reduced downtime and efficient operation of the system. This paper presents an investigation of fault signatures in online condition monitoring methods, focusing on mechanical fault diagnosis of PMSM driven systems. Angular Shaft Misalignment and Mass Unbalance faults are investigated under two different severity levels. Three axis vibration, acoustic emission, stator currents, axial and radial stray flux and shaft torque are evaluated for fault detection, severity assessment and fault discrimination. In the first place, a theoretical framework describing the influence of the specific mechanical faults on the mechanical and electromagnetic behavior of the PMSM is established, enabling the identification of characteristic fault-related signatures. An experimental test bench is developed, integrating a PMSM with vibration, current, stray flux, acoustic emission and torque sensors. Fault signatures are analyzed in both nominal operating condition and variable speed and load levels. Moreover, load and speed transients are investigated. Finally, to extract the most informative sensors, a data driven approach with Mutual Information, Random Forest and Shapley Additive Explanations is employed. Results from this experimental investigation highlight the trade-offs between diagnostic performance, practical implementation and the effectiveness of combining domain knowledge with data-driven approaches for accurate, early and cost-effective PMSM fault diagnosis.