The integration of dielectric inserts into hafnia-based ferroelectric stacks has emerged as a promising route to expand memory windows in ferroelectric NAND. However, the physical origin of the associated coercive voltage enhancement has remained unclear. Here, we resolve this long-standing question by demonstrating that coercive voltage enhancement originates from resistive voltage division between the ferroelectric and dielectric layers, governed primarily by leakage in both layers. Combining Preisach modeling, defect-based Ginestra simulations, and polarization switching experiments with external leaky dielectrics, we show that minimizing leakage in the dielectric layer - intrinsically through wide-bandgap, low-electron-affinity dielectrics or extrinsically by reducing defect densities - provides a universal design principle for coercive voltage control. Importantly, nucleation-limited switching kinetics remain unchanged across the heterostructures, confirming that the enhancement is driven by resistive voltage division rather than trap-assisted mechanisms. This discovery establishes a straightforward framework for engineering large memory windows using ferroelectric-dielectric heterostructures, thereby enabling multi-level (TLC/QLC) operation in 3D NAND. Beyond memory applications, our findings also explain the contrasting behaviors of fluorite- vs. perovskite-based ferroelectric-dielectric systems, offering fundamental guidance for interfacial materials design in next-generation electronic devices.
The explosion of big data has spotlighted the bottlenecks of data movement in traditional von-Neumann architectures. Data analytic applications, such as online analytic query processing (OLAP) databases, are especially burdened by these bottlenecks, given that latency is a key driver in these workloads. Thus, these applications turn to specialized hardware to overcome these otherwise insurmountable challenges. While there are many hardware options, processing in memory (PIM) techniques have gained relevance due to their recent availability as commodity DDR DRAM devices and their relatively cheap expected cost (in terms of power, area, and monetary considerations). However, even with such prevalence, existing research has yet to explore the impact of PIM on end-to-end OLAP workloads fully. In this work, we consider every aspect within a database system; the storage and memory layout, operator implementation, and the data sharing considerations. In particular, we find that ensuring data layout interoperability between query operators is an under-explored consideration that has a significant impact on performance. Using the Star Schema Benchmark, we show that for conservative PIM hardware, up to $17.1 \times$ query latency improvement can be achieved over a state-of-the-art, CPU-focused DBMS.
Abstract This study investigates structural defects in silicon wafers resulting from hydrogen plasma treatment, which is employed to modify mechanical properties within a thin surface layer. Hydrogen-induced defects in silicon have been extensively studied for their roles in doping regulation and defect passivation. The "smart cut" method, utilized in the fabrication of silicon-on-insulator (SOI) devices, involves generating a high concentration of defects at a designated depth to enable the exfoliation of a silicon layer and its subsequent attachment to a substrate. Hydrogen plasma treatment serves as a more moderate technique compared to ion implantation for creating subsurface defects. The principal outcome of this process is the formation of H-platelets. Microstructural observations obtained via transmission electron microscopy are presented to provide a comprehensive overview of the impact of hydrogen RF-plasma treatment on silicon wafers and to distinguish the specific features of hydrogenation-induced defects from conventional structural defects in silicon.
Abstract Accurate transmission electron microscopy (TEM) characterization of photoresist (PR) is limited by preparation-induced artifacts that distort native morphology and obscure failure mechanisms, leading to unreliable root-cause identification in advanced-node failure analysis. We introduce an approach that decouples PR characterization from these artifacts by applying an ultra-thin (~10–20 Å) conformal CVD oxide deposited near room temperature (~30 °C). The oxide stabilizes the PR throughout FIB lamella preparation and low-dose TEM imaging, suppressing deformation, charging, and shrinkage while preserving intrinsic morphology. We benchmarked this method against common protection strategies, including M-Bond, standard Pt and Ir coatings, and e-beam-assisted deposition. All produced pronounced PR deformation and profile distortion from preparation and beam interaction rather than the native structure. In contrast, the low-temperature oxide improved profile measurement accuracy by ~7% and achieved a TEM imaging success rate near 99%. By removing artifact-driven ambiguity, the method reveals intrinsic process-induced PR damage that conventional workflows can mask or misinterpret. In a production case with a 12.5% yield loss, the distortion-free evidence enabled accurate root cause identification, redirected process development, and reduced yield loss to 0.3%. This approach turns PR TEM characterization into a reliable basis for correlating nanoscale structure with process-induced failure mechanisms.
Maintaining consistency between architectural design and runtime-observed behavior is challenging in long-lived safety-critical firmware. This paper presents a runtime-informed methodology for detecting architectural drift in ISO 26262-compliant firmware. The approach collects hardware-assisted execution traces, abstracts them into message exchanges among firmware components, and compares the resulting runtime behavior with design-time sequence diagrams through a deterministic differencing step. The computed delta identifies discrepancies as confirmed, missing, additional, or inverted, while a constrained LLM-based step generates a human-readable report only to support expert review. We evaluate the methodology in an industrial firmware context through agreement-based validation and a practitioner survey. Results over 26 test cases show strong agreement between the generated deltas and expert-curated references, while practitioners perceive the reports as useful for interpreting drift, reducing manual analysis effort, and supporting safety-oriented documentation activities. The findings suggest that combining runtime trace analysis, deterministic architectural differencing, and constrained LLM-based reporting can practically support architectural drift detection in evolving safety-critical firmware.
