Copper (Cu) thin films are critical interconnect materials in advanced semiconductor interconnect and packaging applications, where mechanical reliability under loading conditions relevant to semiconductor manufacturing and packaging becomes increasingly important with continued device scaling. However, the coupled effects of film thickness, loading condition, and microstructure on the mechanical behavior of substrate-supported Cu films remain insufficiently understood. In this study, the thickness- and loading-condition-dependent mechanical properties of Cu thin films are systematically investigated using nanoindentation experiments integrated with finite element analysis (FEA)–based inverse modeling. Cu films with thicknesses of 0.1 μm, 0.5 μm, and 0.9 μm were characterized to evaluate Young's modulus, hardness, effective fracture toughness, and yield strength. The results show that Young's modulus increases from 72 GPa to 117 GPa while hardness decreases from 3.5 GPa to 2.1 GPa with increasing thickness, indicating a transition toward bulk-like behavior. At a peak load of 500 mN, the effective fracture toughness of 1.116 ± 0.156 MPa√m and 3.085 ± 0.593 MPa√m were obtained for the 0.1 and 0.5 μm films, respectively, whereas no measurable surface cracking was observed for the 0.9 μm film. For the 0.1 μm film, the effective fracture toughness decreased from 2.004 ± 0.200 MPa√m to 1.116 ± 0.156 MPa√m as the peak load increased from 100 mN to 500 mN, while no measurable cracking occurred at 20 mN. These observations demonstrate that the measured indentation-derived fracture response is sensitive to both film thickness and the applied indentation loading condition. Yield strength, extracted via inverse FEA, decreases from 500 MPa to 300 MPa with increasing thickness, qualitatively consistent with concurrent grain coarsening and Hall–Petch expectations. These results demonstrate the capability of the integrated experimental–numerical approach to consistently characterize the effective mechanical properties of substrate-supported Cu thin films. In addition, preliminary trend-based grain-size correlations are developed to relate mechanical properties to microstructural features, providing a practical first-order engineering correlation framework for materials optimization and reliability assessment in advanced semiconductor packaging.
We share early experiments with software development for shared CXL memory on the H3 Falcon C5022 CXL switch. We describe how the different stages in the development of a commercial RAG pipeline were impacted by the presence of CXL memory. All of Wikipedia is split into 46 million text passages which are embedded into a high-dimensional embedding space and subjected to heavy load in single- and multi-host experiments. We observe significant performance advantages available to DuckDB and Faiss without changing the software; we measure up to 12x latency reduction with real workloads and 40x reduction with synthetic workloads on CXL, compared to the same queries run with demand paging on NVMe. We explain the current challenges of working with two disjoint cache coherency domains and explain how the Fabric-Attached Memory File System (famfs) and famfs producer-consumer queues provide synchronization patterns without atomic operations on current x86 CPUs. We then discuss open challenges remaining for high performance atomics and locking mechanisms in shared memory. Lastly we show how famfs page-level interleaving enables near-linear throughput scaling when a second host serves queries from the same Faiss index on shared fabric-attached memory and how shared memory allocations can be orchestrated by Kubernetes in a full vertical RAG deployment.
Read disturbance phenomena, such as RowHammer and RowPress, are well-known causes for data corruption in DRAM memories, which have been shown to constitute exploitable security vulnerabilities. Indeed, both phenomena alter the memory locations nearby a row that is targeted by an attacker, potentially leading to writing data in memory locations that should not be accessible by her. In this work, we take a constructive point of view on the read disturbance phenomena. Observing that the data alteration patterns depend on the single device instance, we characterize them with the intent of building a Physically Unclonable Function (PUF). To this end, we specifically analyze the repeatability of data alteration and the information content of the bitflip patterns in modern DDR5 DRAM memories. This analysis would also enable a PUF implementation fully contained within the DRAM module. Our experimental results on multiple DDR5 DRAM chips show that the bitflip patterns caused by read disturbances are remarkably stable when considering a single DRAM row, and are essentially independent across rows in the same bank, or across different devices. These results, combined with a significant information content coming from the unique bitflip pattern produced by a read disturbance, suggest that read-disturbance-based PUFs are promising candidates for future implementations.
Memory disaggregation is an emerging technology that decouples memory from traditional memory buses, enabling independent scaling of compute and memory. Compute Express Link (CXL), an open-standard interconnect technology, facilitates memory disaggregation by allowing processors to access remote memory through the PCIe bus while preserving the shared-memory programming model. This innovation creates a tiered memory architecture combining local DDR and remote CXL memory with distinct performance characteristics. In this paper, we investigate the architectural implications of CXL memory, focusing on its increased latency and performance heterogeneity, which can undermine the efficiency of existing processor designs optimized for (relatively) uniform memory latency. Using carefully designed micro-benchmarks, we identify bottlenecks such as limited hardware-level parallelism in CXL memory, unfair queuing in memory request handling, and its impact on DDR memory performance and inter-core synchronization. Our findings reveal that the disparity in memory tier parallelism can reduce DDR memory bandwidth by up to 81% under heavy loads. To address these challenges, we propose a Dynamic Memory Request Control mechanism, MIKU, that prioritizes DDR memory requests while serving CXL memory requests on a best-effort basis. By dynamically adjusting CXL request rates based on service time estimates, MIKU achieves near-peak DDR throughput while maintaining high performance for CXL memory. Our evaluation with micro-benchmarks and representative workloads demonstrates the potential of MIKU to enhance tiered memory system efficiency.
Multifunctional electronic tattoos (e‐tattoos) integrating energy harvesting, charge storage, and biosignal monitoring are critical for advancing wearable electronics. Most current technologies specialize in one or two functions, lacking a unified, skin‐compatible solution. A novel e‐tattoo is reported using electrospun poly(vinyl butyral‐co‐vinyl alcohol‐co‐vinyl acetate) (PVBVA) fibers coated with titanium carbide (Ti 3 C 2 T x ) MXene. A single electrode triboelectric nanogenerator (TENG) was fabricated via a layer‐by‐layer method using a PVBVA/Ti 3 C 2 T x /PVBVA (PMxP) sandwich structure, and achieved an open‐circuit voltage of 250 V, short‐circuit current of 2.9 µA, and power density of 250 mW m − 2 (25 µW cm − 2 ) under a 2 MΩ load, enabling triboelectric energy harvesting from human motion. A parallel‐plate capacitor using PVBVA/Ti 3 C 2 T x electrodes and a PVBVA dielectric exhibited 14 pF capacitance at 10 kHz and 5 V, suitable for low‐power touch‐sensitive applications. Additionally, PMx‐based e‐tattoos captured real‐time electrocadiogram (ECG) and electromyography (EMG) signals with high skin conformability and minimal signal degradation. The device maintains mechanical flexibility, biocompatibility, and adhesion over extended wear. This scalable, non‐invasive platform demonstrates robust multifunctionality and durability, offering a promising route toward integrated, self‐powered wearable systems for health monitoring, human‐machine interfaces, and energy autonomy. The PMxP architecture represents a significant step toward all‐in‐one e‐tattoos that meet the demands of next‐generation electronics.
