Networks-on-Chip (NoCs - Networks-on-Chip) have emerged as the best alternative to provide high performance in communication for futures Systems-on- Chip (SoCs) with dozens of cores integrated on a single silicon die. However, the components of a NoC are susceptible to faults resulting from heating, power surge, external radiation and others. Faults in a router or a network link can lead to the transfer of erroneous data or, depending on the nature of the fault, cause problems in routing packets, such as forwarding a packet to an incorrect destination or even prevention of a particular path network is used, resulting in system failures. A fault tolerant NoC should be able to detect a fault and prevent it from leading to a system failure, ensuring the correct operation of the application. This paper presents the implementation of techniques for detection and recovery of faults in a NoC, which were modeled in SystemC and validated by simulation. Results compare the effectiveness of two techniques to provide fault tolerance to a NoC.
This article proposes a model for resource discovery directed to ubiquitous computing with technologies for semantic processing aggregated to its architecture. The EXEHDA-SD contributes to increase the expressiveness of the representation and consultation for resources in a ubiquitous environment. The mechanism considers the dynamics in which resources enters or leaves the environment and pursue issues such as scalability and user preferences. The semantic processor and other components of the architecture of the mechanism are described as central contributions of the work.
The evolutionary algorithm NSGAII was applied to the problem of cache memory hierarchy optimization, considering unified second level. The proposed multi-objective approach considers two main objectives: energy consumption and performance related to the number of cycles necessary to run an application. Experiments done with 18 applications from two benchmarks (Power Stone and Mibench) permitted to conclude that found solutions, when NSGAII is applied, are close to optimal solutions. Results also were compared with an existing heuristic (TECH-CYCLES) and was observed that the quality of results obtained are superior in all analyzed cases, being in average 187 times lower in terms of the cost function (FC=Energy x Cycles) that represents the two components: energy and cycles of the application. Evaluating the impact in terms of number of simulations and obtained results, could be noticed that NSGAII needs only 1% of search space, becoming competitive for architecture exploration with unified second level.
This work describes a proposal for a platform focused on modeling and simulation (sequential or distributed) of quantum algorithms. More specifically, the integration between the environments VPE-qGM and VirD-GM is considered, providing a solution to the high computational cost associated to the simulation of quantum algorithms on classical computers. In this context, the algorithms are visually programmed and the details of distribution, communication and synchronization, required for the execution in distributed systems, are transparently managed by the execution environment. The validation and performance analysis consist in simulating a quantum search algorithm, obtaining results which demonstrate the performance gain of the platform compared to the sequential simulation.
The design of new architectures can be simplified with the use of retargetable instruction set simulation tools, which can validate the decisions in the design exploration cycle with high flexibility and reduced cost. The increasing system complexity makes the traditional approach to simulation inefficient for today's architectures. The compiled simulation technique makes use of a priori knowledge about the application to accelerate the simulation with high efficiency. This paper presents a retargetable compiled simulator with three optimization techniques and taking advantage of new GCC optimizations to improve the performance. Three architectures were modeled and tested, MIPS, SPARC and PowerPC. Our MIPS model achieved the best results, with average of 651 million instruction per second, and only 2.8 times slower than native execution.
Several parallel routing algorithms have been proposed during the last three decades. However, most algorithms have been not implemented. Therefore, the execution time and memory resources have been neither measured nor reported. This work presents two parallel routing algorithms for Omega multistage networks by using hardware assistant approach. Both algoritms have been mapped on a FPGA. The first algorithm minimizes the execution time and it is based on a priority encoder. The second one otimizes the hardware resources by using embedded FPGA memories. Omega networks are blocking and some permutations are not completely routed. Extra levels increase the routing capability by doubling the number of paths. This work evaluates the route capacity as a function of network workload, parallel networks and extra levels. Network switches with 2 and 4 inputs/outputs have been taken into account. For each connection, the first algorithm spends only two clock cycles by using the priority encoder. For the second algorithm based on memories, the number of cycles per connection ranges from 2 to 10 and the average number of cycles is around 5.
With the fast evolution of the computing devices, its reduced size and cost, there is an immersion of people in the digital world. With the use of more technology, abundant and cheap, environments that can take advantage of the ubiquitous computing emerge, allowing its users to interact and have access to information easily, quickly and naturally. However, classic ubiquitous environments were defined needing a large installed infrastructure to work properly, something that is not a reality nowadays. This work presents an alternative to the classic ubiquitous environments: a model of services connectivity called Ubiservices, that focuses on providing connectivity to environments made up of unstructured Ad Hoc networks.
The research presented in this paper has as main purpose the conception of a mechanism to control the adaptations the context of component-based applications in Ubiquitous Computing, considering the context produced by monitored information, semantic information and inferences from these informations. The premise is to culminate in a model of adaptation, which can be used both by middleware services, as by applications. For this we propose the use of the concepts and technologies related to Semantic Processing and Autonomous Systems in designing a mechanism for control of dynamic adaptation. The conceived model has compared his contributions to the state of the art, and was evaluated by two case studies, with satisfactory results as to meet the demands of ubiquity.
Quantum computing is a novel way to perform computation based on quantum physics. Since its beginning, at 1985, it promises a revolution in the data processing. Works that have been done prove that quantum computing, regarding its features provided by quantum physics, offer high data processing power compared with classical computation. The aim of the present work is to develop a quantum circuit to perform the signal correlation of Brazilian Decimetric Array (BDA), a radio interferometer that has been developed by National Institute of Space Research (INPE). It was studied some possible circuits and they were compared with classical ones, with respect to the number of logical operations needed to perform the correlation, over a 100 ms integration period. The results show that the proposed quantum circuit uses less logical operations than the classical circuit. Although we don’t have yet technology to build quantum computers, with the same efficiency of the semiconductors, it may be feasible in the future, so that the proposed implementation makes sense.
The mobile and ubiquitous computing has been stimulated by the widespread diffusion of mobile devices, wireless networks, and, more recently, by location systems. In this context, applications are emerging in different areas, such as, education, entertainment, and commerce. The application of the ubiquitous computing in the exploration of business opportunities is called Ubiquitous Commerce. This paper proposes the UbiTrade model, which aims at supporting the ubiquitous commerce. Considering the related works, we can note that the proposed model is the only that allows the user to act either in the supplier role or in the consumer character. In addition, most of the current proposals are restricted to a specific area of business. The UbiTrade does not have this restriction. The model was implemented and its validation was conducted by a group of users. The results indicated the model feasibility, particularly in regard to its most significant contribution, that is, the integration of the support to the roles of supplier and consumer.
The main contribution of this work is the development of a distributed memory architecture for the Distributed Geometric Machine Environment (D-GM) by using a distributed shared memory software implementation (DSM) named ShareD-GM. This work considers the use of the Terracotta system, based on its characteristics which meet all the requirements to implement the distributed memory of the D-GM environment. The development of the ShareDGM contributes to a better dynamical execution with major functionality. The evaluation of this integration was made by the Jacobi algorithm case study. The execution of such method in the proposed implementation and in the previous implementation of the D-GM environment allowed for comparison between the runtimes and speedup, attesting an effective performance improvement
The MMP is an algorithm for image compression which uses the multiscale method of recurrent patterns, based on dictionary. The MMP has compression ratio at the same level of others compression algorithms which are based on transforms, having been detached to images with high frequency, however its execution time has been shown high, by repeated searches of these patterns in dictionaries. In this paper we propose a parallel and dedication hardware to accelerate the execution of MMP, and it is implemented in FPGA, which performs the critical function in 340ns, achieving a speedup of 300 over software version.
Process mapping is a technique widely used in parallel machines to provide performance gains by improving the use of resources such as interconnections and cache memory hierarchy. The problem to find the best mapping is considered NP-Hard and, in shared memory environments, there is the additional difficulty to find the communication pattern, which is implicit and occurs through memory accesses. In this context, this work aims to improve the performance of parallel applications that use shared memory. For that, it was developed a method for analysis of the shared memory which identifies the mapping without requiring any previous knowledge of the application behavior. Applications from the NAS Parallel Benchmarks (NPB) were used in these experiments, showing performance gains of up to 42% compared to the native scheduler of the operating system.
On this work we evaluate scheduling strategies usually applied on heterogeneous distributed environments, taking into consideration the characteristics of opportunistic grids. On the explored scenarios, several parameters are considered and correlated, such as application arrival rate, the occurrence of failures, application tasks size and heterogeneity, and the time to recover from application failures.
In this work, we present two parallel heuristics that coordinate the application of many local search procedures to the Minimum Cost Hop-and-root Constrained Forest Problem (MCHCFP), a Combinatorial Optimization problem in which the minimization of the communication costs in a wireless sensor network with constrained delay and number of hops is desired. The coordinated application of local search procedures in parallel must take into account that these search procedures may have different goals, since the MCHCFP requires the minimization of trees and routes. The presented ideas can be generalized to other problems in which a similar situation occurs.
Bag-of-Tasks applications are parallel applications composed of independent (i.e., embarrassingly parallel) tasks that do not communicate with each other, may depend upon one or more input files, and can be executed in any order. Each file may be input for more than one task. A common framework to execute BoT applications is the master-slave topology. In this paper we studied the scalability of BoT applications running on multi-node systems (e.g. clusters and grids) organized as master-slave platforms, considering two communications paradigms: multiplexed connections and efficient broadcast. We prove that the lower bound on the isoefficiency function for master-slave platforms is achievable by those platforms that have an efficient broadcast primitive available. Our study employs a set of simulation
Technological innovations constantly emerge in computer systems. Its primary focus is on the improvement of performance. One way to improve performance is to increase the hardware. However, this increase in hardware has its implications, like a larger area required on the chip and a consequent increase in power consumption. This boost in power consumption raises heat dissipation, difficult cooling and circuit expansion, among other factors. Because of these problems, the power consumption is target of several studies which try to estimate it and find alternatives to reduce it before the design of the chip. In this context, this paper presents the D-Power tool, a tool described in VHDL designed to estimate dynamic power consumption in components of the fetch stage and cache hierarchy in a superscalar architecture. Based on the entries parameters, the tool is able to verify, among several models of components, which one are more advantageous in relation to power consumption and performance.
Ray tracing is the primary technique used for imaging based on the simulation of physical phenomena. The core problem is in the need of high computing power. Since the 1960s, research has been conducted to improve the efficiency of algorithms and the development of parallel systems has promoted their implementation. Migration to many-core architectures and in particular the development of GPUs make realtime applications possible. This work aims at improving the performance of ray tracing with support for anti-aliasing using image processing techniques implemented in GPU. The results show considerable gains with the use of the proposed approach.
Computer simulation has allowed the analysis of behavior and performance of systems still in its design phase. The Advanced Superscalar Simulator project is a tool for simulation of a complete computer system, involving the simulation of a superscalar processor and an input and output system, with infrastructure for symmetric multiprocessing. It can also run an operating system in the simulated hardware, making the environment more close to reality. The processor simulator is designed so that it can run multiple instruction sets, and it currently supports x86-64. The input and output system contains hypothetical devices of keyboard, video, hard drive and timer interrupt controller. An operating system was designed to manage the simulated hardware. It provides control of interruptions, multiprogramming, virtual memory and a subset of the Linux system calls, therefore, being partially compatible with binaries generated for Linux. The simulator was validated through experiments with the Spec 2000 Benchmark and proved its applicability as a tool for performance analysis
This paper presents a simulation study of the FB scheduling policy in the presence of system loads of varying intensity and variability. The FB policy is compared with the policies FCFS, PS and SRPT, under the same conditions, in mono and multiprocessor environments. The results show that the policy FB is very appropriate for extreme situations, in which there is large variability in service time workload and high load intensity
