Gate-level power estimation based on foundry-supplied standard cell libraries is a common analysis step during digital design. Surprisingly little is known about the accuracy of this approach and the suitability for different circuit types. At the same time, commercial tools implementing this approach are employed broadly and often regarded as the reference when comparing estimation methodologies on higher levels of abstraction. This work evaluates the suitability and accuracy of gate level power estimators for combinatorial circuits of different logic depths in order to test the ability of handling real gate delay effects. While the basic methodology leads to estimation errors of up to 32 % for the tested circuits, by various improvements in the work flow the accuracy can be improved at the cost of longer runtimes. Apart from recommendations on improving accuracy this work identifies shortcomings in the established approach and highlights circuit characteristics that tend to influence estimation accuracy.
Phoenix MapReduce is a programming framework for multi-core systems that is used to automatically parallelize and schedule the programs based on the MapReduce framework. This paper presents a novel reconfigurable MapReduce accelerator that can be augmented to multi-core SoCs and it can speedup the indexing and the processing of the MapReduce key-value pairs. The proposed architecture is implemented, mapped and evaluated to an all-programmable SoC with two embedded ARM cores (Zynq FPGA). Depending on the MapReduce application requirements, the user can dynamically reconfigure the FPGA with the appropriate version of the MapReduce accelerator. The performance evaluation shows that the proposed scheme can achieve up to 2.3x overall performance improvement in MapReduce applications.
Next Generation Sequencing technologies produce huge amounts of short reads consisting randomly fragmented DNA base pair strings, while assembling poses a challenge on the mapping of short reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a many-core hardware acceleration platform for short read mapping based on hash-index method, which benefit from a distributed memory interface with 3D-stacked architecture for local memory access. Our design provides an amazingly 45012 times speedup over software approach for single end short reads and 21102 times for paired end reads, while also beats similar single FPGA solution for 1466 times in case of single end reads.
Power consumption has become one of the major concerns in embedded systems design, especially for mobile devices, which integrate many applications leading to a high power consumption. In this context, designers have the challenge to identify power issues early in the design flow and to explore the largest possible space of power-efficient solutions. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach is based on a high-level modeling of power estimation and dynamic management aspects targeting an automatic generation of the corresponding simulation code. It was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile. The existing C++ simulation code generator was extended in order to integrate power estimation. The main objective of this article is to illustrate the potential of our approach through an MPEG-2 case study. The proposed high-level power modeling concepts were used to target two different platforms for the implementation of an MPEG-2 decoding application. The processor power estimates obtained from simulations were compared to real board measurements. This comparison showed that our MDE approach is capable of obtaining results that can be used to make early power-efficient design decisions.
Simulation techniques cannot cope with the distributive and reactive nature of Network on chip (NoC) architectures very well and thus compromise on the accuracy of the analysis results. Formal verification has been used to overcome these challenges but, to the best of our knowledge, has been mainly used for the verification of packet-switched NoC's. The main focus of this paper is on the formal verification of circuit-switched NoC's, which provide a dedicated channel for all communications with full bandwidth and thus are found to be more efficient than packet-switched NoCs in many contexts. In particular, the paper presents a generic methodology for the formal verification of circuit-switched NoC using the SPIN model checker. The proposed methodology provides generic modelling guidelines and identifies some properties, including deadlock freedom, starvation freedom, mutual exclusion and liveness, that are quite useful in the context of circuit-switched NoC. For illustration purposes, we use our methodology to verify the programmable NoC (PNoC) architecture, which is one of the most widely used circuit-switched NoC.
This papers presents the design of a Network-on-Chip (NoC) simulator for design space exploration of router architectures. The simulator supports cycle-accurate router models and in addition allows the simulation of router architectures, which can adjust their processing according to the traffic type. Realistic traffic patterns are derived from task graph models of real-world applications that are simulated in parallel to the NoC at transaction level. Combining cycle-accurate router simulation and abstract task graph simulation circumvents the limitations of most NoC simulators, which either use synthetic traffic patterns or unrealistic and fixed router models. The proposed simulator architecture is presented in detail and its suitability is shown by means of a case study.
This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.
We have proposed a processor called Auto-Memoization Processor which is based on computation reuse. Until now, we have implemented the auto-memoization mechanism on a single-issue non-pipelined SPARC processor and studied the processor. The processor dynamically detects functions and loop iterations as reusable blocks, and memoizes them automatically. In addition, the processor can apply computation reuse to the blocks with a little reuse overhead. However, the fine evaluation result of the processor may not guarantee enough practicality. This is because instead of such a simple architecture, superscalar architectures are now widely used for generic processors for PCs, embedded processors, and other various processors. Hence, we examine problems which will be caused in the case of implementing the auto-memoization mechanism on an ARM-based superscalar processor and design the ARM-based Auto-Memoization Processor. For example, one of such problems is that pipeline stalls are caused because of the reuse overhead. To solve this problem, we implement a mechanism for overlapping the reuse overhead and the pipeline execution of the processor. The evaluation result with SPEC CPU95 benchmark suite shows that the ARM-based Auto-Memoization Processor can also achieve speed-up as well as the previous SPARC-based Auto-Memoization Processor. In this paper, we describe the implementation and the evaluation result of the ARM-based Auto-Memoization Processor.
This paper presents a new work-in-progress tool, WOKE, to capture and present the workflow model in a novel way. A workflow model consists of linked steps to describe how actual work is done in a company and usually used for analysis and simulation. The complexity of modern System-on-Chip designs motivates applying such enterprise oriented models to the embedded design process domain as well. For example, UML Activity diagrams, YAWL, BPMN2.0, and flowchart descriptions have been used to capture the product design processes. They support very complex models, but that also leads to several different views that complicate the usability and comprehension. The key idea in WOKE is a very rapid creation and editing of the workflow by textual input, separate real-time graph visualization, comparison, and automatic summaries. User can select which details are visualized. Layout is automated and currently it uses a single column for all tasks and transitions. WOKE is implemented in C++/QT5 and is available as an open source tool. A proof-of-concept case study is shown for an FPGA-based SoC design.
This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. In order to efficiently exploit parallel processing and cooperation of the individual components, a System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1 GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system. The proposed system can be useful as a special hardware peripheral or a part of an embedded system.
3D stacking technology provides defined connection impedance and wide and flexible interface. These options enable new architecture approaches and memory concepts for DRAM layers. The most important findings on memory usage is locality principle. This principle is formulated as thumb rule therefore exact rate requires measure for given application using trace driven simulations. This big overhead is useless if application is unknown. Averaging and estimation offer solutions here. This work presents Fast Memory Region - a memory concept that provides an universal 3D DRAM hardware architecture that exploits locality principle for any application. The configuration step, in contrast to cache, is located in software. We evaluate the concept on JPEG2000 algorithm and show that, for encoder procedure execution, all necessary measure data can be extracted from short trace driven simulation runs. Simulations results show 5% reduction of run time overhead compared to cache acceleration only.
For computational tasks with regular data access patterns, e.g. vector arithmetic, single instruction multiple data (SIMD) processor cores present a viable alternative to application-specific integrated circuits (ASICs). Even though the additional flexibility of a programmable core comes at the expense of reduced area- and energy efficiency, this price is potentially worth paying in application domains with a multitude of standards and use cases as it is the case in the domain of wireless communications. The high dynamic range of values that occurs in multi-antenna wireless baseband processing calls for the use of numerical stabilization measures like QR factorization and scaling when operating on a fixed-point processor core. A floating-point core on the other hand covers a wider dynamic range, rendering such measures unnecessary at the price of increased power consumption. This work compares a floating-point and a fixed-point SIMD core in a case study of linear MIMO detection. After evaluating the numerical precision requirements, the achievable throughput of both cores is compared along with the maximum achievable area- and energy efficiency for several use cases, resulting in an assessment as to which number format is best suited for which use case.
We present the hardware architecture and extensions of an Input-Output Memory Management Unit (IOMMU) utilized in heterogeneous SoCs that support full virtualization. The proposed IOMMU architecture offers unique innovative features supporting multiple concurrently active virtual machine instances (VMs) with zero-latency world-context switching and enabling address translation services for up to a thousand virtual domains while serving multiple devices. At the same the proposed design allows for serving multiple address translation requests in parallel and per domain Translation Look-aside Buffer (TLB) invalidation.
In this paper, a dedicated runtime management unit, called CoreManager, is presented. It controls a heterogeneous Multiprocessor System-on-Chip (MPSoC). Therefore, it dynamically schedules tasks on the available processing elements. Furthermore, it is responsible for memory as well as power management. The instruction set architecture of the CoreManager is extended to improve performance for dynamic data dependency checking, task scheduling, processing element (PE) allocation and data transfer management. A significant performance improvement can be shown for all components. Performance results are presented, analyzed and compared with RISC and ASIC based approaches. The integration of the CoreManager in the Tomahawk2 MPSoC silicon prototype is shown. Furthermore, area, timing and power consumption results are provided.
As demonstrated by the recent attack on Intel's Ivy Bridge processor, the traditional Logic Built-In Self-Test (LBIST) methods do not provide adequate protection of SoC against malicious modifications known as hardware Trojans. In this paper, we introduce a simple but efficient countermeasure against hardware Trojans which exploits non-zero aliasing probability of LBIST. We propose to generate LBIST test patterns based on a configurable key which is decided and programed into the circuit after the manufacturing stage. Since the key and hence expected LBIST signature are unknown at the manufacturing stage, an attack based on selecting suitable values for the Trojan which result in the same signature as a fault-free circuit signature becomes infeasible.
This paper presents an implementation of Multicore Communications API (MCAPI), with focus on portability, stability, and simplicity of the design. The main motivation for the implementation is instability of other publicly available implementations. The developed implementation utilizes POSIX message queues, that is an easily portable interface and readily compatible with MCAPI. The performance was measured as latency and transfer rate of the API. The measurement platforms were a x86-64 PC and a development board featuring an ARM processor. A MCAPI implementation was used as reference for comparison. PMQ-MCAPI is much more stable and easily usable than other MCAPI implementations publicly available for PC. When transfer size was between 1-8 KiB, latency of transfers between cores was between 9-15 μs and transfer rate 500-5000 MBps. This translates to 27 000-45 000 cycles and 0.16-1.67 bytes per cycle. CPU and especially performance of its cache were concluded as the most important factors contributing to the performance. In comparison to the reference, latency of the implementation was 1/8 at best, while transfer rate was up to 35x.
This paper introduces a self-optimizing processor/coprocessor model supported by a feedback control system to achieve power efficiency. The software on the processor receives high-level performance constraints (i.e., real-time limits) as goal from the user and in return controls the clock speed of the coprocessor and memories, ensuring the performance constraints are met while minimizing power dissipation. The system is prototyped on a Stratix-V Field Programmable Gate Array device. The self-optimization feature requires less than 0.5% of the overall logic resources and provides a 33% reduction in average dynamic power dissipation when the control system activates for a proof-of-concept test case derived from Fast Fourier Transform processing at the IEEE-802.11n demodulator.
Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulated-annealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%.
Data path widths in state-of-the-art Turbo decoder implementations depend on estimates for the upper bounds of the dynamic ranges of processed metrics. Aiming at highest area and energy efficiency, this paper presents guidelines for designing SISO and Turbo decoder data paths with minimal widths. This is based on least upper bounds for the dynamic ranges of internal metrics within the underlying Max-Log-MAP algorithm. Least upper bounds are presented for the LTE Turbo decoder. Furthermore, a new dynamic branch metric saturation scheme is presented in order to optimize the hardware utilization by proper adjusting the correlated upper state and branch metric bounds. In total, a data path width reduction of two bits is achieved applying radix-4 Max-Log-MAP arithmetic. An overall area-energy complexity reduction of 33% is achieved for the SISO decoder and of 28% for the LTE Turbo decoder.
Nowadays Smart Power technologies are demanding smarter devices to give the opportunity of end-user customizations to reach best-in-class efficiency in applications such as sensing and power conversions. Reconfigurable devices - in the form of embedded FPGA (eFPGA) - can represent an effective solution to address such demand. Differently from CMOS world, where reconfigurable technologies have been widely proposed in the last two decades to couple flexibility and NRE costs reduction, eFPGAs targeting Smart Power applications is a new challenge that we can face today thanks to recent improvement of the digital capabilities of such technologies. In this paper we explore the implementation of a soft-core eFPGA tailored for Smart Power applications targeting STMicroelectronics BCD9s 0.11 μm technology. Area-optimized and speed-optimized implementations prove the existence of a significant design space, both in terms of area (~15%) and speed (~50%) variation. A set of benchmarking applications representative of different smart power fields (sigma-delta modulation, power management and motion control) have been mapped on a 16 CLBs eFPGA; the performance are discussed showing the potential added-value provided by reconfigurability.
