Les réseaux de neurones convolutifs (CNN) utilisés pour l’analyse des signaux vidéo sont très gourmands en calculs. De telles applications embarquées nécessitent des implémentations efficaces en termes de coût et de puissance. Ce chapitre présente une solution basée sur un processeur de jeu d’instructions spécifique à l’application (ASIP) qui représente un bon compromis entre efficacité et programmabilité.

ConvAix is an application-specific instruction-set processor (ASIP) that enables the energy-efficient processing of convolutional neural networks (CNNs) while retaining substantial flexibility through its instruction-set architecture (ISA) based design. By utilizing a combination of data-level parallelism (DLP), instruction-level parallelism (ILP), and subword parallelism, the proposed design offers sufficient processing power for the execution of state-of-the-art CNNs in real-time. ConvAix's arithmetic logic units (ALUs) are C-programmable, thereby offering the degree of flexibility required to implement many different convolution layer types, e.g., depthwise-separable convolutions and residual blocks, as well as fully-connected and pooling layers. It comprises a total of 256 ALUs and leverages low-precision computations down to 4 bits. Furthermore, it exploits sparsity in feature maps and weights via zero-guarding of redundant computations to maximize its energy efficiency. The processor was implemented in a modern 28 nm CMOS technology operating at 1V supply voltage with a resulting clock frequency of 513 MHz. The final design offers a precision-dependent peak throughput between 263 GOP/s (int16) and 1.1 TOP/s (int4), while consuming between 972mW and 340mW of power, resulting in effective energy-efficiencies ranging from 176 GOP/s/W to 2 TOP/s/W. Well-known CNNs, such as AlexNet, MobileNet, and ResNet-18, are simulated based on the placed and routed netlist, achieving between 233 (AlexNet) and 69 (ResNet-18) frames-per-second for a batch-size of 1, including times for off-chip transfers.

Machine intelligence, especially using convolutional neural networks (CNNs), has become a large area of research over the past years. Increasingly sophisticated hardware accelerators are proposed that exploit e.g. the sparsity in computations and make use of reduced precision arithmetic to scale down the energy consumption. However, future platforms require more than just energy efficiency: Scalability is becoming an increasingly important factor. The required effort for physical implementation grows with the size of the accelerator making it more difficult to meet target constraints. Using many-core platforms consisting of several homogeneous cores can alleviate the aforementioned limitations with regard to physical implementation at the expense of an increased dataflow mapping effort. While the dataflow in CNNs is deterministic and can therefore be optimized offline, the problem of finding a suitable scheme that minimizes both runtime and off-chip memory accesses is a challenging task which becomes even more complex if an interconnect system is involved. This work presents an automated mapping strategy starting at the single-core level with different optimization targets for minimal runtime and minimal off-chip memory accesses. The strategy is then extended towards a suitable many-core mapping scheme and evaluated using a scalable system-level simulation with a network-on-chip interconnect. Design space exploration is performed by mapping the well-known CNNs AlexNet and VGG-16 to platforms of different core counts and computational power per core in order to investigate the trade-offs. Our mapping strategy and system setup is scaled starting from the single core level up to 128 cores, thereby showing the limits of the selected approach.

In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e.g. in the well-known ImageNet challenge. As a result, great effort is being put into developing fast and efficient accelerators, especially for Convolutional Neural Networks (CNNs). In this work we present ConvAix, a fully C-programmable processor, which - contrary to many existing architectures - does not rely on a hard-wired array of multiply-and-accumulate (MAC) units. Instead it maps computations onto independent vector lanes making use of a carefully designed vector instruction set. The presented processor is targeted towards latency-sensitive applications and is capable of executing up to 192 MAC operations per cycle. ConvAix operates at a target clock frequency of 400 MHz in 28nm CMOS, thereby offering state-of-the-art performance with proper flexibility within its target domain. Simulation results for several 2D convolutional layers from well known CNNs (AlexNet, VGG-16) show an average ALU utilization of 72.5% using vector instructions with 16 bit fixedpoint arithmetic. Compared to other well-known designs which are less flexible, ConvAix offers competitive energy efficiency of up to 497 GOP/s/W while even surpassing them in terms of area efficiency and processing speed.

Modern process automation and the industrial evolution heading towards Industry 4.0 require a huge variety of information to be fused in a Cyber-Physical System. Important for many applications is the spatial position of an arbitrary object given directly or indirectly in terms of data that has to be processed to obtain position information. Starting point for the idea of the technical reflection-based sound localization system presented in this paper is the biological role model of humans being able to learn how to localize sound sources. Compared to other forms of sound localization, this nature-inspired method has no need for high spatial and temporal accuracy or big microphone arrays. Possible applications for this system are indoor robot localization or object tracking.

Machine Learning techniques such as Support Vector Machines (SVM) have found applications in many fields, e.g. in Wireless Sensor Networks (WSN) and sensor data processing in general. Especially in the case of WSN energy is very limited as agents solely operate based on battery power after they have been deployed, therefore energy efficiency is of great importance. Furthermore, agents are supposed to adapt to their environment by being capable of re-training themselves based on feedback they get from their surroundings, which increases the computational demands on the digital hardware involved. To meet these demands, dedicated hardware in form of a very-large-scale integrated (VLSI) circuit is a reasonable approach and is investigated here. In this paper a specific variant of the SVM — the Least-Squares SVM — is implemented as VLSI circuit. Additionally during the training phase a subset-selection technique based on the quadratic Renyi entropy is implemented in order to reduce the computational and hardware demands. The resulting design consumes 21.35 mW and requires an area of 81.2 kGE without memories.

Large scale antenna systems (LSAS) in the mmWave bands provide a solution to the problems of spectrum shortage experienced in the conventional microwave bands. In a practical large scale antenna deployment, implementation of hybrid beamforming structures is very important as it provides high array gains to overcome the high path loss and achieve sufficient link margins. However, while implementing this we encounter the challenges such as complexity, cost and energy consumption. In this paper a power consumption model for the large scale antenna mmWave system is presented and analysed. From the power consumption model we maximize the energy efficiency of the overall system. Optimization of energy efficiency is a crucial factor in system optimization and design of the power-hungry devices. But with increasing energy efficiency, the spectral efficiency decreases. Thus analysis of the relation between energy and spectral efficiency becomes a critical task and we optimize energy efficiency at a fixed spectral efficiency. The results can then be utilized to guide the practical energy/spectrum efficiency trade-off for the LSAS design.

For computational tasks with regular data access patterns, e.g. vector arithmetic, single instruction multiple data (SIMD) processor cores present a viable alternative to application-specific integrated circuits (ASICs). Even though the additional flexibility of a programmable core comes at the expense of reduced area- and energy efficiency, this price is potentially worth paying in application domains with a multitude of standards and use cases as it is the case in the domain of wireless communications. The high dynamic range of values that occurs in multi-antenna wireless baseband processing calls for the use of numerical stabilization measures like QR factorization and scaling when operating on a fixed-point processor core. A floating-point core on the other hand covers a wider dynamic range, rendering such measures unnecessary at the price of increased power consumption. This work compares a floating-point and a fixed-point SIMD core in a case study of linear MIMO detection. After evaluating the numerical precision requirements, the achievable throughput of both cores is compared along with the maximum achievable area- and energy efficiency for several use cases, resulting in an assessment as to which number format is best suited for which use case.