A reference noise rejected current mirror with a fast start-up mechanism is proposed in this paper. A very low frequency pole, which is 7.2-kHz in this design, can be implemented at the bias circuit so that noise coming from bias generating circuits can be heavily filtered. A fast start-up mechanism by moving that 7.2-kHz pole to a much higher frequency is also proposed to speed up its turn-on process. This fast start-up mechanism reduces the start-up time from more than 100-mu s to 0.2-mu s, and it consumes no steady current after start-up. Simulations show that the proposed circuit can reject the reference noise significantly, ease the noise design of the reference generating circuit, consume no DC current in operation, achieve a fast start-up, and occupy a small chip area.
The Bus Switch mechanism is a recently proposed bus encoding technique for low-power off-chip data buses. The approach is based on clustering, reordering and encoding the bus input lines according to a reordering pattern and a fixed coding function. This work presents a statistical approach for reducing the hardware overhead of the bus switch technique, by operating with a sub-set of the possible reordering patterns. We demonstrate the effectiveness and robustness of the proposed approach by ANSI C simulations, measuring the average switching activity savings. Our results show a modest switching activity degradation while saving 90% computation time, thus obtaining a sub-optimal encoder configuration satisfactory for a large variety of benchmarks.
In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called “Adaptive Edge Filtering Operation (AEFO),” which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total me mory references for loading and storage is reduced by 34% and 36% respectively.
A simple method for the design of FIR filters is presented. It is based on small tables of transition-band samples we optimized for various passband/stopband ripple ratios. The required table, corresponding transition samples and filter order can be selected from the desired passband/stopband ripple, attenuation and transition bandwidth. The samples in the frequency domain can be used for recursive filter realization which consists of comb filter cascaded with a bank of resonators. Such realization in some applications may be considerably more efficient than convolution. Proposed design is simple and fast with sufficient accuracy, as by window method. It offers, however, better attenuations, because the transition samples are optimized here for various passband/stopband ripple ratios.
A low power current-mode analog to digital converter suitable for equipment are required low voltage, low power (ADC). It uses a quartzite level with current injection technique to increase the speed of current mirrors. And this method to reduce the required input signal for a given range and higher operating speeds.In this paper, the feasibility of current-mode algorithmic ADC is demonstrated and advantages of various 2 techniques for use in the converters are considered. Experimental results for 4-bits algorithmic ADC using a 0.8 mu m CMOS technology are reported, including power consumption.
in this paper, a universal filter is proposed using a single first generation current conveyor and minimum number of passive components, such as two resistors and two capacitors. The filter circuit exhibits high output impedance, so it does not need another current conveyor to provide high output impedance terminal for cascading.
In this paper, we explore that bikers apply the pedaling force to the pedal under two type inclined road conditions. Because the road associated with the inclination of the sloping surface, the pedaling force is applied inconsistently to the pedal. Then the biker is easily felt uncomfortable and inefficiency. Therefore, we proposed a control method which based on the sensory system to overcome these issues. The system mechanical, electromechanical, and control design are comprehensively taken into consideration in our article. Finally, the simulation and experiment are executed in our prototype bicycle, CTUbike. Some practically experimental and simulation results are also illustrated to show the validity of our proposed method.
The high data-rate communication channels represent one of the most power-aware design problem, trying to decrease energy consumption maintain acceptable some other performance constraints. In this context, the bus-switch mechanism represents a novel and efficient bus encoding approach for low-power data off-chip buses. It is based on tentatively encoding, clustering, reordering and encoding a wide data buses according to a reordering pattern and a fixed coding function. Unfortunately, the hardware complexity limits the field of application in high capacity off-chip buses, where dynamic energy saving dominates the encoding power consumption. The paper addressed the design issues for bus-switch systems, employing industrial MOSFET models up to 90nm. Additionally, we evaluated the basic hardware resources: area, latency and power dissipation. Results indicated how future CMOS technologies enhance the bus switch’s field of application.
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible, robust and comprehensive tool that can evaluate k-ary n-cube based network topologies under non-uniform traffic patterns. The simulator provides full control over essential network parameters and flow control mechanisms such as virtual channels and sub-channeling. We compare three low-dimensional k-ary n-cube based interconnects that can fit into the physical limitations on line cards, where each one of these interconnects has multiple processor-memory configurations. Performance results show that k-ary n-cube architectures perform better than existing interconnects, and they can sustain current line rates and higher. In addition, we provide performance tradeoffs between multiple flow control mechanisms and performance metrics such as throughput, routing accuracy, failure rate and interconnect utilization.
A novel low power architecture and integrated circuit is presented for applications in the analog baseband processing section of next generation wideband direct conversion wireless receivers. The proposed system features current mode signal processing for filtering and analog to digital conversion as well as large programmable gain to handle the large signal variations present in wireless designs. The use of current mode signal processing allows low voltage and low power operation and addresses the design concerns in modem mobile terminals that aim to reduce energy consumption for enhanced battery life. An experimental circuit that demonstrates the feasibility of designing such a system consumes only 5 mW of power at 1.5 V with an input dynamic range of 60 dB, a noise figure of 25 dB and linearity better than + 1 dBm at maximum gain setting in SiGe technology.
Color distortion is less noticeable than noise and blur. Normally color distortion, especially found in the low bitrate JPEG images, does not need to be corrected until it is above the level of JND (just noticeable distortion). The first part of this paper presents a comparative assessment of color distortion in different color spaces for blurred images. Experimental results show that color distortion increases as the magnitude of motion blur increases, and remains in the same level as the window size of Gaussian blur increases. The second part presents two color correction methods: One is RCC (Referenced Color Correction) and the other is NRCC (No-Reference Color Correction). Experimental results show that RCC can correct distortion by 88.3 % and NRCC can correct distortion by 60.71 %. The distorted images can be enhanced to have better perception.
With shrinking feature size, increasing frequency and chip density, power dissipation on data bus has become the most predominant factor than the power dissipation in other parts of the circuitry. Further de facto, the inter-wire capacitance has become the dominating factor in Deep Submicron Technology (DSM) compared to substrate capacitance. So, the earlier schemes of minimizing the substrate capacitances are not valid in these buses. By taking these facts into account a novel bus coding technique is proposed in this paper which reduces the inter-wire capacitance by 14% for 8, 16 and 32 bit bus compared to unencoded bus. The proposed method divides the bus lines into two groups and selects that grouping which yields the minimum inter-wire capacitance.
The paper deals with the tracking of an endangered Hawaiian bird (nene) and real time display of the GPS location in a GIS environment. The project has been implemented as a working prototype for investigating an integrated model for environmental research, which concentrates on the application spatial, and temporal analysis techniques to large-scale ecological data sets and includes satellite imagery and ground-based sensor data. The primary objective of the paper is to present the current state of the art for capturing and displaying live location information of a moving target in a wildlife environment.
A novel calibration scheme for predistortion Sigma Delta PLLs is proposed in this paper. In contrast to present calibration algorithms this technique offers a digital representation of the high frequency phase characteristic. The architecture uses minimum chip area by synchronously sampling the data content of an asynchronous divider chain. Using this tech. nique to detect the phase difference during a step response allows to determine the real loop gain within 7 mu s with an accuracy better than 0.1%. Obtaining this, the deviation from the desired loop gain can be adjusted by a digitally controlled charge pump in order to derive the wanted loop transfer function. This is mandatory for predistortion modulation loops. The architecture is designed by systemthe-oretical calculation of the loop behaviour and verified by mixed signal VHDL-AMS simulations.
We apply the proper eigenvalue procedure to a system of two concentric rotating cylinders enclosing a viscous fluid. The linear partial differential equations that rule the system in the absence of gravity, and in the low Reynolds limit, are solved a) analytically, b) through direct space and time iteration, and c) by using the eigenvalue procedure which avoids numerical time iterations. In this method the time dependent response of the system is obtained directly from the trivial Laplace transform inversion, once the zeros and poles of the system are known. The method arises from the analysis of the Laplace transform of a given variable (the velocity of the liquid in the present paper), as given by application of the determinant rule according to Cramer. The determinants involved are evaluated efficiently in terms of a generalized eigenvalue problem, which determines the poles and zeros for the system. We compare the computational time required in the three approaches, showing the advantages of the eigenvalue calculation. This approach might be particularly useful in engineering and science teaching in multidimensional problems since it not only saves computer time, but also provides a valuable physical insight through the knowledge of the pole and zero constellation.
A 4-Gb/s half-rate clock and data recovery circuit (CDR) with a 3-stage voltage-controlled oscillator (VCO), and a novel phase/frequency detector (PFD) is reported in this paper. The VCO produces multiple-phase clocks spaced by one-third of the incoming data symbol period. A novel PFD is employed to compare the multiple-phase clocks with the incoming data and produce the error signals to tune the VCO frequency with the aid of a charge pump and a loop filter. The PFD also produces a signal to enlarge the charge pump current during the frequency acquisition stage so that a fast frequency acquisition can be achieved. This CDR was implemented in CMOS 0.18 mu m technology and its feasibility was confirmed by post-layout simulations.
The transfer process of active power, the interchange of reactive power, and optimization ratios, related to DC-DC buck-converters are analyzed. The proofs of optimization of some criterion functions of power consumption for arbitrary DC circuits are given. The criterion function of the powers in converters is determined. This function indicates the tendency to maximization of the consumed active power and, at the same time, to maximization of the reactive power circulating between the reactive elements, which returns to the power supply. The state function of the process of power exchange is introduced. The similarity between the power increase and increase of entropy is established. The returned power is corresponding to negentropy. The defined functions allow characterization of electrical circuits from the standpoint of order, disorder and irreversibility of processes.
Chaotic signals can be used to spread narrow band information over a wider frequency spectrum due to wideband characteristics of chaotic signals. One important aspect of performance of any spread spectrum communication system is the ability to resist jamming. In this paper, we attempt to drive general analytical BER for coherent CSK modulation system under a multiple access techniques for multi user noisy and jamming environment (MA-MCSK). The chaotic signals for the users can be derived from a given map with different initial conditions, or they can generated from different maps. Analytical bit error rate (BER) is derived, permitting evaluation of performance for a range of noise level, jamming power, jamming frequency and spreading factor that minimizes the bit error rate.
The framework described in this paper uses an array of FPGA devices to implement a virtual hardware system that can be compared to the running of software on a traditional processor. Virtual Hardware is achieved by using the Field Programmable Gate Array (FPGA) technologies with on the fly partial programmability feature. The similarity between page size selection in a virtual storage system and selection of optimal area size for FPGA reconfiguration are compared and contrasted. Communication issues between modules that are mapped onto various parts of the FPGA are compared to the software engineering paradigms dealing with module coupling, fan-in, fan-out and cohesiveness. Finally, the overhead associated with the downloading of the reconfiguration files and potential for fault tolerance is examined in comparison to traditional operating system design choices.
This paper presents an accuracy and high speed PC based Heart Rate Monitor and analyzing the Heart Rate, which is implemented in Xilinx FPGA (Field Programmable Gate Array). An Analog to Digital Converter 100 MSPS (mega samples per second) used for a design high accuracy and high speed PC based Heart Rate Monitor. Personal computer is interfaced with Analog to Digital converter through Xilinx FPGA. Using Xilinx FPGA, Hardware part of FIFO (First In First Out) and UART (Universal Asynchronous Receiver and Transmitter) are designed by VHDL coding in Xilinx FPGA. The aim of the project is to display the graphical representation of heart rate pulse wave form onto the computer by 'C' programming and analyzing the Low and High Frequency by derivative Threshold algorithm using MATLAB programming. An ordinary Heart Rate Monitor has been replaced by PC based Heart Rate Monitor in many applications, as represents as wideband, high speed, high resolution and storage. It is more powerful, reliable, flexible and commercially marketability.
