This paper presents a simulation based approach to decompose the overall conducted RF emission of a complex integrated circuit (IC) into partial emission spectra due to various functional blocks or processes in the analyzed DUT IC. The approach is described based on a generic power switch.
This paper reports the functional behavior of a system consisting of a pressure sensor within its sensor module, a two-wire supply with current modulated communication channel and an electronic control unit equivalent during powered system-level ESD tests. It discusses functional recoverable soft-failures, their failure mechanisms and root causes considering overall system properties as well as special electro-mechanical integrated circuit properties, and ESD test requirement and procedures.
This paper presents a method for determining the appropriate sensing resistance value when measuring integrated circuit (IC) noise in DC-DC converter ICs using the 1 Omega method as outlined in IEC 61967-4. By modeling the DC-DC converter circuit as an equivalent RLC resonance loop and accounting for the parasitic inductance of the sensing resistor, we established the permissible range for the sensing resistance. Through circuit simulations, this study examines the impact of sensing resistance and parasitic inductance on the ringing noise of DC-DC converter ICs, ultimately determining the optimal resistance value for accurate IC-level noise measurement.
Introducing a new high-speed design requires a careful optimization of any discontinuities that may degrade signal quality. A high-speed signal includes structures such as BGA (Ball Grid Array), vias, AC coupling capacitors, or connectors. Poorly matched impedance may result in undesirable signal reflections, energy losses, and electromagnetic interference. These structures need to be wisely optimized in order to limit signal reflections along the path while taking into account manufacturing constraints, costs, performance and routing density for avionics products. However, with each new design change during the various stages of development, major modifications can challenge previous optimization choices. Therefore, it is crucial to create adaptive and flexible models that can easily evolve with these changes. The objective is to develop a library of optimized models that can be seamlessly integrated into internal routing tools and efficiently reused for future designs. Three types of mathematical algorithms were studied based on the objectives, constraints, performance, and time required to converge toward the best design in order to automate this time-consuming process.
To analyze IC destruction and malfunction due to ESD (IEC61000-4-2), we proposed an on-chip current sensor that can accurately capture the entire ESD current waveform flowing into the IC that oscillates significantly for positive and negative in the nanosecond range. Measurement accuracy has improved by compensating for measurement errors caused by voltage overshoot in the nanosecond range of the current detection device. The ESD current waveform flowing into the IC is different from the standardization waveform, and a positive and negative oscillation waveform can come in, and we have designed to handle these polarities. This sensor sets a design window that does not incorrectly respond against noise that does not affect the system, and it only captures ESD currents of ampere or more. This sensor will become an important component for analyzing IC destruction and malfunction due to ESD.
Side-channel attacks, which estimate the internal secret key by analyzing the radiated electromagnetic waves generated by the current consumption of the encryption circuit, represent a realistic threat. To achieve resistance against side-channel attacks, the current consumption of the encryption circuit must be independent of the secret key. In circuit design, side-channel resistance should be evaluated by simulation to reduce rework costs. For this purpose, a highly accurate power model for logic cells is needed to represent the minute differences in power consumption that vary with input during the encryption process. However, in ASIC design and FPGAs, models are provided only to estimate overall power consumption. In this paper, we propose a method to extract the power consumption of a single logic cell with high accuracy from power consumption measurements of multiple same logic cells to avoid background noise, and show that the increase in peak power consumption with the number of elements when NAND logic is implemented is captured linearly. This measurement method archives express the difference in power consumption caused by the different directions of logic transitions.
This paper examines the use of spread spectrum clocking approaches to reduce the increasing electromagnetic emissions caused by the constantly rising switching frequencies of modern electronic systems. The approach to reducing these emissions is based on spreading the spectral power of a narrowband signal over a certain bandwidth in order to reduce the peak amplitude. We will compare the performance of a spread spectrum clock generator based on the random method with one using simple frequency modulation with a triangular modulation signal and relate it to their theoretical behavior. Furthermore, we will perform CISPR-compliant emission measurements with different detectors of an EMI receiver and compare the influence on the measurement results.
Loop inductances offer decisive advantages over partial inductances when electromagnetic systems shall be modeled in a compact and understandable manner. This publication builds on a previously published mathematical technique to extract physical "white-box" models from S-parameters of systems comprising, e.g., power IC metallization, interposers, IC-packages, PCBs and an environment. We shown how a complex system can be segmented by means of differential source and sink ports, forming a multigraph. The ports should be arranged in order to minimize the number of large magnetic couplings by reducing loop area and overlap. We discuss practical examples, such as striplines, half bridges, discrete coils and segmented ground planes. The technique supports development of CMOS SoCs, integrated Automotive ICs, fast-switching DC/DC-converters and high-power modules (SiC MOSFETs, GaN HEMTs).
Embedded systems exhibit variability in emitted EMI when executing different instructions. To further analyze EMI signals and identify their correlations with the internal behavior of a specific DUT (an FPGA-based microcontroller), an improved algorithm for processing clock signals is proposed to recover distorted clock waveforms. This approach allows for more accurate and stable FPGA-based microcontroller EMI signal segmentation and analysis. This technique can provide technical support for electromagnetic information leakage security analysis in embedded systems.
In this paper, we analyse the robustness of operational amplifiers (OpAmps) against electromagnetic interference (EMI). Therefore we compare a standard folded cascode amplifier structure with an EMI-improved amplifier structure introducing a cross-coupled double differential input pair. We perform measurements on the manufactured test chip structures to determine general characteristics (gain, offset, gain-bandwidth product (GBWP) and phase margin), as well as EMI-related characteristics (EMI-induced offset respectively electromagnetic interference rejection ratio (EMIRR)). Based on these characteristics, we compare both structures with regard to their performance. Further on, we put the measurements into relation with our previous findings that we obtained from simulation.
Compound power semiconductor devices such as Silicon Carbide (SiC) and Gallium Nitride (GaN), are increasingly being adapted into automotive, renewable energy, and energy management applications to advance carbon neutrality. These devices offer the advantage of operating at higher switching frequencies than their silicon-based devices, attributed to their superior switching speed and reduced on-resistance. The ability to operate at elevated switching frequencies also enables the realization of high-power density in DC/DC converters. However, with the widespread application of compound semiconductor devices capable of high-frequency operation, the importance of noise reduction generated from power converters is significantly increasing towards safe and secure societies. Consequently, this paper presents the latest advancements in noise reduction methods based on a comprehensive literature review. This paper introduces strategies for common-mode noise reduction in high-power and high-frequency applications without necessitating an increase in the converter's volume.
GaN power transistors offer significant advantages with respect to Si ones, but introduce challenges in meeting EMC regulations due to their high switching frequencies. This paper compares two modulation schemes, Spread-Spectrum Modulation (SSM) and Sigma-Delta Modulation (Sigma Delta M), for reducing the conducted Electromagnetic Interference (EMI) delivered by GaN-based DC-DC converters. The study analyzes how these techniques impact converter performance and evaluates their effectiveness in reducing conducted EMI at low frequencies. The findings provide valuable insights for designers seeking the most effective strategy for EMI mitigation.
Boundary conduction mode (BCM) current control is an emerging soft-switching technique in single-phase grid-connected inverters. However, the significant ripple in inductor current leads to heightened electromagnetic interference (EMI) noise in form of differential mode (DM) noise. This paper proposes an analytical model to predict the differential mode EMI noise for BCM based single-phase grid-connected inverter, which can facilitate the design of the EMI filter without repetitive measurements. Experimental validation is conducted on a 500 W hardware prototype to affirm the feasibility and efficacy of the proposed model.
Threats arise when malicious circuits, known as hardware trojans (HT), are inserted into information devices, compromising security. These HTs can be inserted during the design and manufacturing process of devices, and thus, methods to detect them at the time of manufacturing have been studied. In recent years, it has been pointed out that HTs can also be inserted into parts such as printed circuit boards (PCBs) even after shipping, requiring detection throughout the lifetime of the device. To address this threat, sensing methods using analog circuits have been proposed, but their application is limited. In contrast, this paper proposes a method using a ring oscillator (RO), which can be generally implemented with digital circuits, to detect electrical changes caused by the insertion of HTs. Specifically, the wiring of the RO configured inside the IC is extended externally, and the changes in propagation delay caused by HT insertion on the wiring are detected as changes in the oscillation frequency of the RO. As a result of confirming the effectiveness of the proposed method through experiments, it was confirmed that the proposed method can be used to detect capacitance changes even when a small HT consisting of only a single transistor is connected to the wiring on the PCB.
The demand for large-scale data samples has always been a significant bottleneck in the application of artificial intelligence methods in the field of electromagnetic compatibility (EMC) of integrated circuit (IC). This paper proposes the Transfer Learning Encoder-Decoder network (TL-ED) method for predicting circuit S-parameters. Considering the high computational cost involved in obtaining accurate high-fidelity data samples, this method utilizes transfer learning to transfer the rough model, which is modeled based on low-fidelity data with low computational costs, to the accurate model. Subsequently, the model is fine-tuned using a small amount of high-fidelity data. Application results confirm that this approach significantly reduces the demand for high-fidelity data and has the potential to be applied in IC-EMC analysis where data acquisition through testing experiments is necessary.
In this work, we investigate the impact of ionising radiation on the robustness towards electromagnetic interference (EMI) of operational amplifiers (OpAmps). Therefore we irradiate two OpAmps, one including a standard differential input stage structure, the other OpAmp featuring a second cross-coupled double differential input pair added to the standard input stage structure. We perform measurements on the manufactured test chip structures to determine general characteristics (gain, offset, gain-bandwidth product (GBWP) and phase margin), as well as EMI-related characteristics like EMI-induced offset and electromagnetic interference rejection ratio (EMIRR). Based on these characteristics, we compare both structures with regard to their performance prior to, during and after irradiation with X-rays. We observe a change in the EMIRR performance with increasing ionising dose. Finally, we explain our observations by taking into account transistor-level effects.
An ICIM-CI model of an analog circuit with a differential amplification for mass production development is proposed. It is observed that manufacturing variations, such as in terms of the oscillation frequency, cause differences in failure thresholds, obtained by the DPI method, between samples. The maximum difference is 8.7 dB at 1.0 MHz. To predict the lowest forward power that causes failure, a prediction formula based on design information is obtained. By comparing the prediction results with measurements, it is confirmed that the forward power can be estimated within the range of variations.
This research paper provides an extensive examination of electromagnetic interference (EMI) in wireline transceiver systems. Wireline transceiver circuits are particularly susceptible to undesired electromagnetic waves in their environment. The paper delves into a mathematical approach for incorporating EMI into circuit simulation tools. Additionally, it explores the impact of EMI on different wireline communication systems, such as LVDS, CML, and PAM-4 transceiver systems. The goal is to comprehensively understand how EMI affects the performance of these wireline communication systems.
This study analyses the Electromagnetic Immunity (EMI) of STT-MRAM. By exhaustively exploring and verifying the Electrostatic discharge (ESD) and Electrical Fast Transient (EFT) of STT-MRAM, the impact of ESD and EFT on the performance of STT-MRAM is investigated, the potential threat of transient electromagnetic interference to STT-MRAM memory is revealed, and suggestions are made to improve its electromagnetic compatibility (EMC), which provides an important reference for its reliable application.
This paper investigates the response of various commercial electrostatic discharge (ESD) detectors with respect to their ability to detect charged device model (CDM) like short pulses and their ability to discriminate between CDM and non-CDM pulses. A series of test setups (TEM cell, sphere-to-Gnd discharge, narrow pulse generator) were set up to evaluate how different detectors behave at different pulse widths and field strengths. Pulse durations varying from 150 ps - 16 ns FWHM were applied in the different test setups. The measured responses of the detectors under different ESD conditions are analyzed and compared.
