Performance of graph algorithms often depends both on the underlying hardware architecture and on structural properties of the input graph. Optimizations that deliver high performance on one class of graphs, such as hypersparse graphs with low average degree, can degrade performance on other classes, for example denser graphs with high average degree. In this work, we investigate sparsity-aware GPU kernel selection for computing the Jaccard similarity index, a measure of neighborhood overlap in graph datasets. In our kernel selection approach, we use the vertex-centric Jaccard similarity implementation from the cuGraph library as the baseline and include both vertex- and edge-centric variants of this kernel, with set-intersection algorithms varying between two-pointer linear search, binary search, and adaptive dynamic search. We use 80 real-world graphs in our evaluation with variation in average degree, maximum degree, Gini index, and average intersection cost. A random forest classifier, trained on a subset of these graphs on an NVIDIA A100 GPU, achieves 88.8% inference accuracy in predicting the fastest kernel. Kernels selected by the classifier achieve a 4.37x mean speedup over the vertex-centric cuGraph baseline from NVIDIA.
Forest fires increasingly threaten ecological integrity, human communities, and infrastructure, with vegetation composition significantly influencing fire behavior, intensity, and spatial dynamics. Accurate characterization of forest ecosystems across multiple taxonomic scales is therefore critical for effective fire prediction models, fuel load assessments, and strategic fire suppression planning. In this context, we introduce a novel hierarchical machine learning framework utilizing the National Data Platform (NDP) [1] to classify vegetation across three distinct ecological levels: Plant Functional Type (PFT), genus, and species. This hierarchical approach aims to provide precise and actionable insights for enhanced fire risk assessment and management.
SimpleScalar is a cycle-accurate simulator that has been used in computer architecture and compiler research, particularly for studying superscalar processors with out-of-order execution. Originally designed to simulate the Alpha and PISA ISAs, it has been extended to support other architectures such as PowerPC, MIPS, and ARM. This paper proposes to retarget SimpleScalar to support RISC-V architecture with RV64GC configuration, which covers a standard set of extensions (G) that are commonly used for general-purpose computing on RISC-V architectures (i.e. I, M, A, F, zifencei, zicsr), and the ISA extension for compressed instructions (C). Furthermore, a hardware optimization technique called macro-op fusion will be incorporated into SimpleScalar to improve performance by combining two or more instructions into a single, more complex instruction during the decoding stage. Preliminary performance evaluation will be conducted by executing MiBench benchmarks on the prototype implementation of SimpleScalar RV64GC.
Power capping, which is an essential component of power oversubscription, has been widely used in data centers to host more servers than allowed by the capacity of their power infrastructures, in order to avoid expensive power upgrade and reduce capital expenses. Traditionally, power capping is performed mainly with CPU frequency and voltage scaling, which cannot be directly applied to the GPU servers that are commonly deployed in today's data centers, because GPUs can have much higher power consumption than CPUs. Recently proposed GPU power capping solutions are designed for a single GPU and so cannot be used on GPU servers that have a host CPU and multiple GPUs to process machine learning (ML) workloads. Hence, a joint power capping solution must be designed to coordinate the host CPU and all the GPUs in a server for optimizing ML inference performance. In this paper, we propose CapGPU, a power capping framework for today's GPU servers that run ML workloads on multiple GPUs and a host CPU in each server. In sharp contrast to existing solutions that try to control the server power consumption by throttling either the CPU or one GPU, in a separate manner, CapGPU features a multi-input multi-output (MIMO) power control methodology and a novel weight assignment algorithm that dynamically adjusts the weights assigned to each CPU/GPU based on their measured throughput. Consequently, the overall ML inference performance can be optimized. Our hardware testbed results demonstrate that CapGPU outperforms several state-of-the-art power capping solutions by having more precise power control, higher inference throughput, and better inference latency guarantees.
Modern distributed file systems (DFSs) rely on metadata server clusters to manage large-scale files and achieve scalability. However, the hierarchical namespace structure and dynamic user workloads pose severe challenges for efficient metadata partitioning and load balancing. Existing approaches primarily focus on identifying and redistributing hot metadata to address imbalances. While these load-balancing strategies offer potential benefits, they often reduce metadata locality, ultimately failing to improve the end-to-end job completion time-a key metric prioritized by users. Although recent research reveals that learning-based approaches are effective in predicting hotspots, they have been shown to be less effective in improving metadata performance. We revisit metadata load balancing strategies and propose a learning-based metadata load balance framework Origami, which focuses on minimizing end-to-end job completion time rather than equalizing loads. Origami first decomposes the overhead of metadata operations and assesses the impact of migration decisions on user requests, allowing us to compute the benefits of migration decisions for job completion time when future requests are known. Subsequently, Origami propose the Meta-OPT algorithm to determine near-optimal migration decisions. Finally, we implemented OrigamiFS, on which we collected statistical data to train and validate ML-models capable of predicting migration benefits. By predicting the benefits of migration decisions and employing Meta-OPT to quickly explore nearly optimal migration decisions, Origami makes a better trade-off between load balancing and namespace locality. Our evaluation shows that compared to state-of-the-art methods, Origami increases aggregated metadata throughput by 1.12-2.51x across three real-world workloads, and enhances end-to-end throughput by 1.11-2.02x.
The rapid growth of deep learning has created unprecedented demand for computing resources, while many small and enterprise-level clusters remain underutilized. Computing resource exchange platforms offer a solution by aggregating these idle resources. However, effective cluster-task matching depends on accurate performance prediction. Existing approaches, which decouple prediction from matching, often lead to suboptimal decisions due to misaligned objectives. We propose a Matching-Focused Cluster Performance Predictor (MFCP), an end-to-end framework that integrates performance prediction with task matching to improve decision accuracy and resource utilization. Unlike existing methods that prioritize prediction accuracy, MFCP minimizes decision regret by aligning the predictor's loss with optimal matching objectives. To handle non-differentiable matching optimization, we use continuous relaxation and incorporate constraints via an interior-point method, ensuring meaningful gradients for training. For non-convex optimization, we approximate optimal decisions with gradient descent and estimate gradients using zeroth-order perturbation. Experiments show that MFCP consistently outperforms existing methods across different cluster environments and scales, achieving lower matching regret and higher resource utilization.
In-transit visualization has become essential in high-performance computing (HPC) to reduce I/O overheads and enable real-time data analysis. However, as simulations grow in scale and complexity, these visualization tasks increasingly demand substantial computational resources, exacerbating energy consumption and limiting system scalability. As we show in this paper, a key bottleneck is the conventional one-rank-per-GPU allocation model, which leads to irregular GPU utilization and waste of hardware resources. To tackle this challenge, we propose using GPU-sharing strategies to improve energy efficiency in in-transit visualization without compromising performance. We evaluate six distinct configurations built upon three NVIDIA GPU-sharing mechanisms: the default CUDA model with context switching between processes, Multi-Process Service (MPS), which enables dynamic context sharing, and Multi-Instance GPU (MIG), which provides hardware-level partitioning. Using the WarpX simulation code and Ascent visualization framework, our experiments on the Polaris supercomputer span multiple rendering techniques, node counts, and data sizes. Results show that GPU-sharing strategies can improve the trade-off between performance and energy, represented by the energy-delay product (EDP) metric, by up to 81.7%. We also show that workload-aware strategy selection is essential to improve performance-energy efficiency: MIG-based configurations are more effective for lightweight and regular workloads, offering up to 64.5% energy savings, while MPS better handles GPU-intensive workloads, achieving up to 71.1% EDP improvement. Finally, we demonstrate that optimized sharing strategies can reduce the required compute nodes by up to 75%, freeing system resources for concurrent workloads.
While load balancing in distributed-memory computing has been well-studied, we present an innovative approach to tackle challenges that an electromagnetic application poses due to irregular workloads and tight memory constraints. To this end, we present a unified model for approximating work in a distributed system that combines three key components: computation, communication, and memory. This enables the exploration of complex trade-offs in task placement, such as increased parallelism at the expense of data replication. We then present our new fully distributed load balancing strategy that incorporates this model. To predict workloads for the matrix assembly of the electromagnetics application, we apply machine learning across an ensemble of executions to train a neural network, which makes online predictions for our task-based decomposition, informing the load balancer of the computational loads. Finally, we demonstrate that our approach, when applied to this application, leads to substantial speedups, up to 2.0x, thereby decreasing time-to-solution for the imbalanced execution.
Ensuring data privacy in blockchain systems remains challenging due to the heavy computational and communication costs of traditional cryptographic mechanisms. Existing solutions often suffer from limited scalability, high resource consumption, and inefficient tamper-proof key management. To address these challenges, we propose Zero Trust Privacy (ZTP), a lightweight framework for scalable on-chain privacy and secure distributed key management. ZTP introduces a hybrid quorum protocol using dynamic scale-free graph adjustments and a parallel data and key management mechanism based on the Geometric Fragmentation Technique (GFT), achieving efficient, tamper-resistant shard handling. To further enhance scalability, we incorporate a lightweight consensus protocol with parallel transaction processing, isolating transactions and key access from untrusted blockchain nodes. We implement and evaluate ZTP on a distributed blockchain prototype, demonstrating outstanding performance, achieving up to 49% fault tolerance, and delivering speedups of at least 55x compared to state-of-the-art blockchain protocols. Our results highlight ZTP's potential for resource-constrained and large-scale blockchain deployments.
Modern supercomputer architectures are diverse and becoming increasingly complex. Scientists are constantly porting code and re-optimizing it for the new architecture, but achieving good performance is challenging. Performance portability programming models such as RAJA, Kokkos, and OpenMP enable codes to maintain a single-source code rather than rewriting for each target architecture. However, portability models alone will not result in optimal performance as hardware has varying specifications (e.g., cache sizes and speeds) and parallel algorithms may use varying amounts of memory and compute resources.We present a systematic analysis of application behaviors across a diverse set of CPU and GPU hardware. We leverage the RAJA Performance Suite, which contains a curated set of kernels commonly found in HPC applications, to perform an in-depth GPU and memory analysis aswell as a quantitative performance portability evaluation across different compute platforms. In analyzing the performance portability scores, we identify gaps and opportunities to achieve consistent performance across platforms. We provide a comprehensive analysis across seven architectures, including the most recent GPU systems with new physical memory layouts, where kernels demonstrate a runtime speedup of up to 44x. Although the speedup highlights the baseline improvements of newer hardware, the performance portability scores calculated, ranging from 0% to 92%, showcase where opportunities remain for scientists to increase utilization of the newer systems.
Modern workloads increasingly rely on GPU acceleration. A well-known performance bottleneck in this context is the warm-up effect, typically observed on the first memory copy call. Our analysis confirms this behavior for large data sizes (above 2 MB), where the initial transfer is notably slower. However, for smaller data sizes, the first call can be faster than subsequent ones, and in some cases, particularly involving memory allocations, the warm-up shifts to the second call. These findings offer new insights into the nuanced behavior of GPU memory instructions and help explain irregular warm-up patterns. By shedding light on these mechanisms, our work supports the development of more efficient and predictable GPU programming strategies.
Superword-Level Parallelism (SLP) vectorization is a widely used compiler technique that transforms straight-line scalar code into efficient vector code by identifying and grouping independent, isomorphic instructions. Traditional SLP implementations typically initiate from store instructions and traverse upward along the defuse chain, making a single, local vectorization decision without being aware of the global knowledge. However, this heuristic strategy can be suboptimal due to the vectorization order, which can hinder performance and vectorization opportunities. In this work, we present a hybrid slice seleciton algorithm that strategically combines dynamic programming with greedy heuristics. This approach enables more informed decisions by analyzing vectorization order and inter-tree dependences, leading to improved utilization of SIMD resources and better overall performance. Our experiments demonstrate significant cost reductions across several standard benchmark suites for both RISC-V and ARMv8 architectures. According to the LLVM cost model, the optimizations yield an additional reduction of up to 67% on RISC-V and 41% on ARMv8.
We hereby present a modular framework for resource-aware instruction through open courselets, aligned with FOUNT guidelines and deployed via the National Data Platform (NDP). The implementation of these materials in the Fire-Ready Forests Data Challenge, which engaged 48 student participants, facilitated hands-on engagement with wildfire data and AI modeling. Participant feedback confirmed the efficacy of courselets in skill development and challenge success, thereby establishing a foundation for broader reuse and future scaling.
Large Language Models have transformed numerous domains with their exceptional capabilities. However, their training processes are inherently prone to failures due to the massive scale of training clusters, involving thousands to tens of thousands of GPUs and requiring several months of uninterrupted computation. Check-pointing serves as a critical mechanism for ensuring fault tolerance. However, the substantial size of LLM checkpoints, attributed to their vast number of parameters, poses significant challenges in terms of time and storage overheads. While existing approaches offer partial solutions, they remain inadequate in addressing the unique demands and complexities of LLM training at scale. To this end, we propose Amber, a novel LLM training framework that significantly improves checkpointing speed and storage efficiency by leveraging selective incremental checkpointing, a technique that selectively checkpoints significant parameter updates while omitting minor changes. We implement Amber atop PyTorch, a widely adopted deep learning framework, and demonstrate that Amber achieves up to 10-155x faster checkpointing compared to state-of-the-art full checkpointing methods across models of varying scales on a single GPU, while maintaining storage overhead below 3%.
Distributed computing systems are essential for meeting the demands of modern HPC applications, yet effectively utilizing distributed environments presents significant challenges. Resource misallocation in shared systems can lead to resource contention, degraded performance, priority inversion, inefficient utilization, and environmental impact. We extend the capabilities of BanditWare, an online recommendation system that dynamically selects the most suitable hardware for applications using a contextual multi-armed bandit algorithm. Designed for seamless integration with the National Data Platform (NDP) [2], BanditWare enables users of all experience levels to optimize resource allocation efficiently while prioritizing low runtimes. In previous work, BanditWare was limited to a linear regression backend model for runtime prediction [4]. In this extension, we introduce the ability for BanditWare to run using one of several available model types with the ability to specify model hyperparameters. This allows BanditWare to more accurately predict the behaviors of complex applications while maintaining its lightweight base whenever possible.
Distributed AI training generates unique low-entropy flow patterns with predictable, singular and repetitive flows that differ fundamentally from traditional network flow with heavy-tailed distributions. While sketch-based methods are widely used for network measurement, existing approaches fail to exploit these distinctive characteristics, resulting in poor measurement accuracy. To address this issue, this paper proposes FP-Sketch, a high-accuracy sketch for measuring low-entropy flows with Flow Prediction. FP-Sketch utilizes a staging queue to predict and classify flows of different sizes, thereby leveraging the singular, repetitive, and predictable nature of low-entropy AI flows. Combined with hierarchical storage, our method achieves superior measurement precision for distributed AI workloads. We establish rigorous error bounds for FP-Sketch through theoretical analysis. The experimental results show that FP-Sketch reduces flow estimation error by 38.6% and improves insertion throughput by 49.4% compared to the state-of-the-art alternatives.
Structured-grid problems are common in scientific computing, particularly in applications like fluid dynamics and electromagnetic simulation. One of the key kernels in solving these problems is Sparse Triangular Solve (SpTRSV), which often becomes a performance bottleneck due to its low computing intensity and inherent internal data dependencies. In structured-grid SpTRSV, the regularity of non-zero distributions and the high parallelism of sparse matrices present opportunities to harness the architectural strengths of modern heterogeneous processors. However, existing SpTRSV algorithms fail to fully exploit these advantages, due to their mismatches in data dependencies, computational order, and memory layouts. In this paper, we introduce a novel SpTRSV algorithm tailored for structured-grids on modern heterogeneous processors. Our approach introduces a two-level blocking strategy to enhance data locality and reduce communication overhead, while a vertical tiling-based pipeline balances parallelism with computational granularity. Additionally, we design hardware-specific adaptive scheduling strategies to accommodate varying degrees of parallelism across distinct architectures. The algorithm has been implemented on two types of heterogeneous processors, NVIDIA GPUs and SW26010-Pro, with hardware-specific optimizations to further improve the performance. Experimental results show that our implementations achieve speedups of more than 1.87x over state-of-the-art baselines and provide efficient end-to-end solutions with lightweight preprocessing.
Near-memory processing can reduce latency and increase available bandwidth but requires extracting memory-level parallelism under strict operating constraints. Many memory-intensive workloads have low arithmetic intensity with often small register working sets and memory access patterns that cause frequent stalls and poor processor utilization. Latency hiding using instruction-level parallelism is limited for such workloads and can incur significant overheads. Instead, multithreading is widely used to hide stalls, but existing methods use large statically banked context storage that can remain underutilized while limiting the number of threads. This paper presents the Virtual Register Context (ViReC) system architecture as a novel performance-area optimized approach for efficient, hardware-assisted dynamic context management and multithreading of memory-intensive workloads on near-data processors. ViReC virtualizes the register file and uses it as a cache for active partial register contexts. To manage the register cache state, ViReC employs a novel Least Recently Committed (LRC) replacement policy tailored to register access patterns of memory-intensive workloads. With ViReC, multiple contexts can be stored within a smaller physical register file that does put a static limit on thread counts where performance degrades gracefully as additional threads are scheduled. We evaluate ViReC on a range of nearmemory benchmarks. Results demonstrate that ViReC achieves 95% of the performance of a banked processor while reducing area by up to 40% and scaling to higher per core thread counts.
Winograd algorithm powerfully accelerates Convolutional Neural Networks. However, for backward-filter convolution (BFC), existing implementations often struggle to achieve both high throughput and low memory usage, due to challenges from large filters and small outputs. We propose WinRS, a fast, memory-efficient, and flexible BFC algorithm. WinRS reduces N-D large filters into 1D formats and precisely splits them to match the fastest kernels. These fully-fused kernels execute BFC in on-chip memory with tiny workspace, leveraging the superior acceleration potential of 1D Winograd. WinRS adaptively balances workloads into an optimal number of block groups, maximizing hardware utilization in small-output cases. When ported to FP16 on Tensor Cores, WinRS achieves 3.27x throughput of its FP32 CUDA-Core version. In experiments, WinRS achieves 1.05x to 4.7x speedup over cuDNN GEMM using comparable workspace; WinRS uses less than 4% workspace of cuDNN FFT and Winograd, and exhibits higher throughput with memory- and FLOP-bound workloads.
