Reliable ultrasonic aluminum wire bonding of cylindrical lithium-ion battery cells depends strongly on the cleanliness and chemical state of the cell terminal surfaces. Residual organic contaminants and native oxide layers originating from manufacturing and handling can impair bond formation and reduce process yield. Laser cleaning is a promising non-contact surface preparation method; however, its effects on terminal surface chemistry and integrity under manufacturing-relevant conditions require further clarification. In this work, a single production-relevant pulsed laser cleaning parameter set was applied to commercially available cylindrical lithium-ion battery cells. The surfaces were characterized in terms of elemental composition, surface morphology, and residual organic contamination using complementary analytical techniques, including XRF, SEM-EDX, and LC-MS. The results show that laser cleaning induces measurable surface changes consistent with improved wire bondability while preserving nickel and aluminum terminal metallization. These findings support laser cleaning as a scalable pre-bond surface preparation method for battery pack manufacturing.
This paper focuses on developing a contactless jetting technique to apply a microparticle-based silver (Ag) sintering paste suitable for pressureless sintering of miniaturized optoelectronic components. Traditional soldering methods are limited by their lower thermal conductivity and the risk of remelting at elevated operating temperature (>200 °C), which can be addressed by employing advanced sintering techniques. We detail the optimization of a contactless jet dispensing process and analyze the influence of key parameters, such as cartridge pressure, needle lift, rising-time, and open-time, on the precision and reliability of material deposition. A volumetric flow model is developed as a qualitative framework to identify parameter dependencies. Through experimental validation using square-footprint LED dice, we demonstrate a linear correlation between open-time and dot volume while highlighting falling-time as a free parameter affecting dot morphology. The reliability of both the developed jetting process and the microparticle-based paste is confirmed through shear testing of LED dies on Direct Copper Bonded (DCB) substrates, achieving shear strengths exceeding 60 MPa after 1000 hours of storage at 200 °C. This methodology demonstrates the potential for the accurate and efficient application of sintering pastes in optoelectronic packaging and paves the way for future advancements in microelectronic assembly.
The continuous scaling of semiconductor devices, driven by Moore’s Law, demands advancements in interconnect technologies. Cu-to-Cu direct bonding has emerged as a critical solution for enabling ultra-fine pitch, high-density interconnections with superior electrical and thermal performance compared to traditional Cu-to-solder joints. This bonding method is pivotal for applications such as 3D integration, FOWLP, and 2.5D/3D packaging, supporting miniaturization, high-speed data transfer, and improved thermal management. However, Cu oxidation during processing presents a significant barrier, degrading bond integrity, increasing interfacial resistance, and complicating backend-of-line (BEOL) packaging integration. To address these challenges, we developed an ultra-thin (2–5 nm) Cu-selective oxide-suppression coating using standard industry-compatible techniques, including chemical vapor deposition (CVD) and liquid-phase deposition (LPD). The coating effectively prevents Cu oxidation during high-temperature thermal compression bonding (TCB) without requiring high-vacuum equipment or costly metal coatings, enabling scalability for heterogeneous packaging. RAIRS-QCM metrology validated the coating’s chemical stability and persistent oxidation resistance even after two months of ambient storage. Oxidation suppression efficiency of ~53% was confirmed by RAIRS characterization following an annealing at ~300°C in ambient air for 1 hour. Bonding evaluations were performed on 5 nm passivated Cu substrates under optimized bonding conditions. Shear testing revealed an average force of 40.7 ± 4.2 kgf/cm 2 , exceeding MIL-STD-883 requirements. Cross-sectional STEM confirmed a defect-free Cu-Cu bonded interface, while STEM-EDX analysis verified that the coating effectively suppressed oxidation without impeding Cu-to-Cu bonding. This work establishes the developed coating as a scalable, high-throughput solution to enhance Cu-to-Cu bonding reliability, enabling next-generation semiconductor packaging with improved electrical, mechanical, and thermal performance.
Despite advances in 2.5D and 3D packaging, ultrasonic wedge (stitch) bonding remains the industry standard due to its cost-effectiveness. However, the transition to copper (Cu) and palladium-coated copper (PCC) wire introduces reliability challenges, traditionally mitigated by expensive and environmentally concerning silver (Ag) plating on leadframes (LF). To address this, we developed a low-cost, ultrathin Cu-selective passivation coating that suppresses oxidation, enabling direct Cu-Cu bonding without Ag. This process-compatible coating was evaluated on Cu-LFs using 25 µm Al-1 wt% Si and PCC wires under varying thermal conditions (125 °C-200 °C). Optimization of bonding force, time, and ultrasonic power yielded substantial improvements in pull strength. Notably, while bare-Cu bonds failed at the oxidized interface, passivated samples failed at the wire neck, confirming superior bond integrity. This work highlights a promising, environmentally sustainable alternative to Ag plating, enabling reliable Cu-Cu stitch bonding for next-generation, low-cost IC packaging solutions.
This study reports, for the first time, the fully additive fabrication of miniaturized, embedded triple-stacked copper spiral inductors—an unprecedented achievement in multilayer inductor manufacturing. Using our novel Sequential Build-Up–Covalent Bonded Metallization (SBU–CBM) method, we demonstrate a etch-free, room-temperature process capable of producing complex 3D inductor architectures with sub-10 μm features and high vertical integration. Unlike conventional additive, subtractive or hybrid subtractive–additive techniques, the SBU–CBM method enables high-resolution laser-defined patterning, selective electroless copper deposition, and accurate optical alignment—completely eliminating the need for vacuum systems, chemical etching, or thermal sintering. The successful fabrication of three vertically interconnected spiral inductors through 10 μm copper microvias confirms the method’s unmatched capability in fabricating intricate multilayer geometries through a fully additive process. Optical microscopy and X-ray Computed Tomography (XCT) imaging validate the structural integrity, precise interlayer alignment, and continuous electrical connectivity across all layers. Critically, the method achieves uniform miniaturized copper strip widths of 10 μm, underscoring its strength in high-density packaging and next-generation integrated systems. This breakthrough establishes SBU–CBM as a transformative approach for realizing compact, high-performance, and scalable 3D embedded components in future electronic applications.
This paper presents a mechanical simulation of image sensor packages, with a particular emphasis on accurately modeling the cure shrinkage and viscoelasticity. Image sensors have a wide application in mobile phones, autonomous vehicles, and medical imaging. They are highly sensitive to warpage and misalignment, which can significantly degrade the image quality. The encapsulant acts as a primary barrier, protecting the sensor from external factors such as moisture and thermal mechanical stress. Accurately modeling and predicting the package warpage is crucial to ensure the optimal optical performance. Previous simulation studies on image sensor packaging often neglect cure shrinkage, leading to inaccurate warpage predictions. Cure shrinkage, a phenomenon where the material contracts during the curing process, can induce significant stress on the package and lead to warpage in addition to CTE-mismatch. This work developed a new simulation approach to incorporating cure shrinkage modeling, and it achieved a much higher degree of accuracy in predicting package warpage, as demonstrated by the close correlation between simulation results and actual warpage testing data. Furthermore, this paper studied the impact of using viscoelastic properties and compared time-dependent deformation with elastic solutions. Finally, this paper conducted comprehensive design of experiments (DOE) studies to evaluate the impact of different encapsulant materials on the susceptibility to glass cracking. The findings of this work are particularly useful for improved warpage prediction in simulation and better understanding of encapsulant properties, ultimately optimizing the package design and enhancing the reliability and longevity of electronic devices.
There have been strong demands for lower power consumption and higher bandwidth in optical/electrical interconnects used for artificial intelligence (AI) and networks in a data center. The adoption of co-packaged optics (CPO) has been expected for both high-performance computing (HPC) driven by AI and high-bandwidth and high-speed communications networks in a data center. In this study, on-board optics (OBO), near package optics (NPO), and CPO will be discussed. Emphasis is placed on 3D heterogeneous integration of chiplets such as photonic integrated circuits (PIC), electronic integrated circuits (EIC), and application specific IC (ASIC) switch w/o bridges on CPO substrates, e.g., organic, silicon, and glass. Some recommendations will be provided.
Gallium-based liquid metals (LMs) are materials that possess some unique properties. Just like any other metal, they have high thermal conductivity and low interfacial resistance, but they are in a liquid phase at room temperature. In contrast to mercury alloys, gallium alloys are non-toxic. They don’t evaporate and they can’t be inhaled. The viscosity of those alloys is very similar to water, but they are six times as dense as water. All those properties make Gallium-based liquid metals very good candidates for thermal interface material (TIM) in electronics applications. On the other hand, the reaction and incompatibility of those alloys with some metals is one of the challenges for this type of TIM. The other challenge is that those materials are not just thermally, but also electrically conductive and that is not a desirable property for TIM. A suitable barrier that will prevent any leakage of LMs and the best way to apply the appropriate volume of LM in high-volume production (HVP) would be one of the most important things for any application. A key challenge is applying the liquid metal consistently through a traditional dispensing method due to its property and behavior which involves high surface tension. Through advanced dispensing techniques like jetting technology liquid metal can be applied reliably on a flat, uneven surface or in arrays of minuscule confined spaces or cavities. This paper highlights the dispensing quality, weight repeatability from one substrate to another, and valve hardware stability. This paper will also address the challenges faced during dispensing of liquid metal in high volume manufacturing, and how to achieve desired bondline thickness with jet dispensing for higher throughput and process reliability.
Additive Manufacturing (AM) and Printed Electronics (PE) have recently seen widespread implementation in numerous technological applications. The shift towards manufacturing AM PE is largely due to the numerous benefits that AM offers compared to traditional manufacturing. Some of these benefits include the ability to rapidly prototype and the reduction of waste material compared to traditional manufacturing methods, and the ability to realize conformal circuits onto existing structures and substrates with varying form factors. In this work, an AM analog temperature and humidity sensor for high temperature applications was designed and printed using a multi-axis tabletop nScrypt printer. Electrical, mechanical, and statistical testing was performed on the circuits to assess the performance and uniformity of the printed circuits.
This study evaluates the thermal performance of Lead Frame, Al₂O₃ Direct-Plated Copper (DPC) Ceramic, and AlN DPC Ceramic packages in Driver-MOSFET(Dr.MOS) devices. Experimental measurements at 12V and 19V under current loads of 0A–40A, along with ICEPAK simulations, confirm that the AlN DPC Ceramic package achieves the lowest thermal resistance (Rthjc = 1.48 K/W) and temperature rise (120.7°C at 19V, 40A). The Lead Frame package exhibits moderate thermal performance (Rthjc = 2.61 K/W, 144.6°C), while the Al₂O₃ DPC Ceramic package shows the highest thermal resistance (Rthjc = 3.33 K/W) and temperature rise (172.8°C), limiting its suitability for high-power applications. These results emphasize the significant impact of packaging materials on thermal management, identifying AlN as the most efficient solution for high-power Dr.MOS applications.
Nanoporous silica waveguides can be used to improve the low sensitivity of near-infrared spectroscopic gas sensors by allowing the light propagating through the waveguide core to interact directly with molecules entering the pores. Here we report on a self-aligned fiber-to-waveguide configuration that offers a robust and cost-effective solution for coupling fibers to the nanoporous waveguide without the need for active alignment or expensive instrumentation. Our approach uses dedicated fiber-alignment structures next to the waveguide, fabricated at the same time as the waveguide, and made from the same material, thus eliminating the need for separate substrates, additional fabrication steps, and minimizing thermally induced optical misalignment. We present the optimized microfabrication process steps that allow for direct insertion of optical multimode silica fibers next to the multimode porous silica waveguide and provide structural and optical characterization. Gas sensing performance is evaluated using isopropyl alcohol vapor showing excellent sensitivity and detection limit of 1.76 ppm for a 10 mm long waveguide.
In this study, two problems of flip chip on glass-core package substrate will be investigated. The first problem deals with the flip chip on glass-core package substrate with microbumps and the other deals with the flip chip on glass-core package substrate with Cu-Cu hybrid bonding. Emphasis is placed on the solder joint reliability due to the glass-core substrate by nonlinear time and temperature dependent simulations, especially for the determination of the warpage of the structure and accumulated inelastic strain of the solder joints. Some recommendations will be provided.
Buried cavities in low temperature co-fired ceramic (LTCC) substrates, whether completely blind or fabricated with ports, are often utilized in industry in areas such as microelectronics packaging, microfluidic sensor fabrication, and microwave resonant chamber creation. These applications often have stringent requirements for cavity volume, parallelism, and wall planarity that are critical for the performance of a given device. While there has been significant research and reporting on the fabrication and functionality of these structures, there is a lack of available literature regarding methods used to mitigate deformation of these structures during the fabrication process while providing for precise dimensional control of the final structure. Although essential processes in the fabrication of LTCC structures, the lamination and sintering steps both pose challenges to creating uniform and precise buried cavities in LTCC substrates: deformation due to high pressure on unsupported green tape structures during lamination, as well as volume loss and deformation during the sintering process. This paper will report on methods, technologies, and processes used to mitigate deformation and allow for precise and repeatable dimensional control of buried cavities in LTCC substrates. Specifically, fugitive materials and rigid cavity inserts will be used in conjunction with the manipulation of lamination pressures and sintering profiles to understand and control the forces resulting in the deformation of these buried cavity structures. The results of these technologies and processes will be examined through cross sectioning and optical inspection as well as through contact profilometry.
In this paper, we demonstrate the direct Cu-Cu thermal compression bonding (TCB) for fine-pitch heterogeneous integration by leveraging a pre-applied underfill making it comparable to the traditional solder-based TCB using non-conductive films (NCF). In contrast to the well-known inorganic dielectric hybrid bonding process for fine-pitch interconnects where the dielectric like SiO 2 is bonded first, followed by Cu bonding in a batch-anneal process, our approach sets forth a single-step process for attaching both the dielectric and Cu pillars. The high costs associated with hybrid bonding process due to its stringent cleanroom requirements, material handling and pre-/post-processing is currently limiting its industry-wide adoption, whereas the use of inorganic dielectric in this case relieves many of the stringent process and infrastructure requirements. The Cu-Cu TCB demonstrated in this paper is carried out in a state-of-the-art high-accuracy TCB tool developed by Kulicke and Soffa Industries (K&S) capable of rapidly heating/cooling the source die, perform in-situ flux-less reduction of Cu oxide using vaporized formic acid, and applying high pressures up to an equivalent of 500 N during bonding. The test vehicles incorporate dielectric material researched by Resonac Inc., which is an organic layer spin-coated and partially cured onto a wafer terminated with Cu pillars followed by a tailored chemical-mechanical polishing process (CMP). The adhesion strength of the bonded dielectric has been experimentally determined at approx. 21 MPa for a 4×4 mm 2 die. For Cu-Cu TCB, the 5.1×5.1 mm 2 source dies consisting of 10-µm-diameter Cu pillars equally spaced at a 20 µm pitch are bonded to target sites on coupons measuring 10.2×15.3 mm 2 . The Cu-Cu TVs bonded and annealed for over 8 hrs at 250°C showed noticeable grain-growth across the interface. As our approach eliminates the requirement of a post-bond underfill, it is a viable solution for scaling heterogeneous integration down to sub-5 µm pitch interconnects.
With the rapid growth of artificial intelligence (AI) and high-performance computing (HPC), the demand for advanced semiconductor technologies continues to rise. These applications require packaging solutions that deliver high performance, reliability, and miniaturization. Modified semi-additive processing (mSAP) has become essential for enabling fine features such as high-density redistribution layers (RDL) and stacked vias in modern IC substrates and printed circuit boards (PCBs). However, several challenges remain in implementing mSAP at scale. One issue is V-pitting, which can occur during the flash etching step, and reduces the mechanical and electrical reliability of copper interconnects. Conventional approaches to mitigate V-pits often involve energy-intensive baking steps, which increase cost and reduce throughput. In addition, traditional plating methods frequently lead to voids, seam voids, and non-uniform copper deposition—defects that undermine reliability and performance. Another key challenge is the dependency of many electroplating processes on specific tool configurations. Such tool-specific formulations can require significant capital investment and limit manufacturing flexibility. In contrast, a tool-agnostic process can be implemented across a range of plating systems, providing cost-effective scalability and easier integration into diverse production environments. Thermal stress is also becoming a critical concern as modern AI and HPC chips, including high-power Graphics Processing Units (GPUs) and Central Processing Units (CPUs), can consume over 1000 W. The resulting heat places significant mechanical stress on the substrate, leading to warpage. Substrate warping compromises the interconnect integrity and can lead to system failure. Therefore, copper deposits must possess the mechanical strength and ductility to withstand thermal cycling. This study introduces an optimized copper electroplating process designed to address these challenges. It uses a bottom-up filling mechanism, which ensures that copper deposition starts at the base of microvias and progresses upward. This approach prevents the formation of voids and seams, which are common in traditional top-down processes. By using a novel combination of additives—commonly referred to as suppressors, accelerators, and levelers—this method achieves a highly uniform, defect-free filling and consistent copper thickness across both die and panel. As IC substrates increase in unit size and the industry shifts toward panel-level packaging, maintaining uniformity across the entire panel becomes critical to ensuring product quality and performance. Importantly, the copper deposited using this process exhibits superior physical properties, including higher tensile strength and elongation. These characteristics enable the substrate to better absorb thermal stress and resist warpage, enhancing long-term reliability in high-power applications. Additionally, the deposit shows high purity with minimal organic and inorganic contaminants. This purity reduces grain boundary weakening and improves resistance to electromigration, which is critical for maintaining interconnect integrity under high current densities in advanced electronic devices. The process is tool-agnostic and works seamlessly with various plating systems, including vertical continuous plating (VCP) and high-speed plating (HSP). This adaptability enables faster adoption without requiring extensive equipment changes. Overall, this plating process offers a scalable, efficient, and robust solution that improves reliability, reduces manufacturing cost, and supports the demands of next-generation AI and HPC technologies.
Residual fluorine on Al wire bond pads of semiconductor wafers has been attributed to the reactive plasma etching of passivation dielectric layers during the bond pad opening process employing hydrofluorocarbon gases. Even though the initial fluorine concentration immediately after pad cleaning processes is typically below 5 at.%, the concentration can increase to a few times higher with prolonged wafer storage times. Higher fluorine concentrations on the Al bond pad surface increases the risk of aluminum fluoride crystal growth, resulting in pad discoloration. The impediment of intermetallic compound (IMC) formation during wire bonding caused by aluminum fluoride crystals on the Al bond pad surface acting as an interdiffusion barrier can lead to process, quality and reliability issues with the semiconductor device. Through this work, the mechanism of increase of fluorine concentration on Al bond pads, the mechanism of aluminum fluoride crystal formation, and the prevention methods are better understood. Transmission electron microscopy (TEM) analysis revealed that disruptions in the native Al 2 O 3 layer underneath the aluminum fluoride crystal form paths for Al supply for the crystal formation and growth, forming depletion voids in the Al surface. The chemical composition of the aluminum fluoride crystals has been ascertained by X-ray photoelectron spectroscopy (XPS) to be AlF 3 . A detailed study of the effects of wafer storage methods on fluorine concentration on Al metallization of test wafers confirmed an outgassing-condensation mechanism occurring inside the wafer storage. Three storage-related factors have been found to influence the outgassing of fluorine compounds from the wafer polyimide passivation and condensation of fluorine compounds on the Al bond pads: humidity level, displacement of fluorine outgassing species by N 2 , and restriction of outgassing by wafer interleaf film. At the wafer fabrication site, storage of in-process wafers (in wafer box or wafer carrier) in a N 2 cabinet shows a much higher effectiveness in reducing the fluorine compound condensation on the Al bond pads. At the packaging assembly site, the wafer canister storage methods (wafer canister sealed in moisture-barrier bag (MBB) with desiccant, and wafer canister in N 2 cabinet) provide adequate protection for finished wafers from Al bond pad discoloration. These wafer storage methods have effectively prevented the occurrence of fluorine-induced Al bond pad discoloration over prolonged wafer storage times in both the wafer fabrication and packaging assembly sites.
Efficient high-performance computing (HPC), especially for applications in the field of artificial intelligence, requires the use of specialized computing and memory chips, short transmission paths and high packing densities. A key technology for HPC is therefore the integration of processors and memory stacks in a single System-in-Package (SiP) using silicon-based interposers. Manufacturing concepts have been developed for such a package, each of which utilizes different process flows to build an HPC module. Following a holistic approach, the process flow is evaluated from the processing of the interposer with high density organic redistribution layers, compression molding and balling. Evaluation methods were defined for the individual process steps and criteria established to enable the selection of suitable process steps and combinations for an optimized package. The process flow options were realized and analyzed for a reference HPC module. An important parameter for all these process steps is warpage, since an exceeding warpage can make processing impossible. For compression molding, a key process step, the influence of different materials and process parameters on the warpage was therefore investigated. The results of the process development are presented for the backend process flow with an emphasis on compression molding process step, an evaluation of the process variants is carried out according to the previously developed criteria and the most suitable variant of the process step for later production is selected on this basis.
Thermal management is key to enabling increasingly powerful chips and heterogeneous integrated 2.5D/3D systems. Composite materials with high thermal conductivities that can be placed at different levels of proximity to the die provide new solutions for heat dissipation. Here we report the fabrication of thick copper-diamond composite films using cold spray, which is a high-throughput, low-thermal budget deposition technology. In cold spray, feedstock micro powder is accelerated in a specially designed nozzle by a heated pressurized gas and adheres to the substrate upon high-speed impingement. This process achieves higher deposition rates than other methods used in semiconductor manufacturing (such as electroplating). It also produces films which are denser and much less porous than ones produced by conventional thermal spray techniques. In this work, we first use process and thermal simulations to determine the requirements of the micro diamond powder feedstock, including the diamond core size, metal clad thickness, the core-clad interfacial resistance and volume fraction to enable the cold spray of copper-diamond composites with thermal conductivities that are higher than copper’s. Subsequently, we perform systematic characterization of the diamond powders from several suppliers, including the purity, metal oxygen content, particle morphology and metal-clad adhesion. This characterization reveals the challenges of meeting all the specs using currently available diamond powders . Finally, we cold spray copper-diamond composite films on a variety of substrates with tunable thicknesses between 100um -2 mm, achieving a thermal conductivity that is approximately 10% higher than cold sprayed pure copper. Further improvement of the thermal properties relies on continued innovation in powder surface modification and powder packaging/shipping methods.
In this article, we present and illustrate a flip-chipbased antenna-on-package (AoP) concept for the development of 5G mmWave massive MIMO antenna arrays and frontend modules. Unlike conventional Antenna-in-Package concepts, our concept provides the flexibility to choose suitable and separate layer stack-ups and packaging materials for enabling the antennas and the frontend components to meet their respective specifications. To illustrate this concept, we designed, fabricated, and measured novel dual-polarized broadband AoP arrays in the 39 GHz frequency band for 5G mmWave MIMO applications. The array consists of 16 identical stacked patch elements. Each single antenna possesses a driven patch, which is vertically stacked to a parasitic element to improve the antenna performance. It is excited by two orthogonal probe-feds for dual polarization. Furthermore, we designed and optimized antenna arrays together with the solder interconnects used for mounting the antennas onto the multilayered interposer. Our results show that these interconnects could cause up to about 0.5 dB reduction in the realized gain of the antenna array. The fabricated antenna arrays were measured from 33 to 41 GHz. A peak gain of approximately 16 dBi was measured. Excellent correlation was obtained between all the measurement and simulation results.
Today’s unique assembly challenges are comprised of complex printed circuit board (PCB) panelization, involving identical PCBs with a goal of increased production capability, due to a reduced footprint of the production floor. Identical PCBs that are within the same panel, with uniform spacing in an array or carrier, need to be dispensed at the same time. All these high-mix challenges have gone mainstream and affect real productivity and throughput. Existing manual dual-head dispensing systems do not consider the rotational correction for the second head, which leads to yield loss. To eliminate the yield loss on the second head, there is a mini XY drive system incorporated that provides fast and accurate dispensing to double the process capabilities over the same work area. Dynamic dual-head (DDH) dispensing uses a unique mini XY drive system on the left head, mounted on a separate Z-axis, to dynamically control the position of the head for accurately aligning to a second part, while synchronously dispensing both parts. The machine vision system performs the substrate alignment for each identical PCB that is individually placed in a carrier, which provides greater potential for variation in offset and skew. During synchronous dispensing for the second part with the DDH all the kinematic adjustment is performed with calculated values, from the skew angle and scaling factor. This technique guarantees increased productivity whilst maintaining yields through unsurpassed accuracy. DDH also provides the same level of adjustment and rotational correction for all step and repeated PCBs, flex circuits, and panel designs. If a product contains an odd number of units, then either of the heads can be programmed for dispensing while the others cannot. This paper examines proven methods to determine the dot/line positional accuracy along with the mass flow rate for both heads during synchronous dispensing. This paper will also address the challenges faced, and how the rotational correction can achieve up to 23 higher throughput than existing single/dual head dispensing systems.
