Hybrid bonding is being evaluated for advanced packaging of 2.5 and 3D modules due to the enhanced scalability and performance (thermal, electrical and reliability) of the interconnect. The direct bond interconnect (DBI®) Ultra technology is a die to wafer hybrid bonding assembly process that uses all die handling on dicing tape frames. We explore the assembly of various die sizes, pad and pitch dimensions to identify fundamental challenges and solutions to accelerate adoption of this technology in manufacturing. In this paper, we discuss the assembly process results of a test vehicle with an interconnect design of 3.5 μm pad on 7 μm pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 1,400 to 520,000 links. The component wafers were diced and transferred to tape frame for subsequent die preparation for bonding. The 3.5 μm bond pad requires sub-micron alignment accuracy within the bonder for 100% alignment yield. However, with careful process control, alignment yield greater than 98% and void free yield of 96-99% was achieved using a bonder with 3 μm alignment accuracy. The die stacks were characterized with electrical resistance measurement, C-mode scanning acoustic microscopy (CSAM), and cross-section microscopy analysis. A process to evaluate the defectivity in daisy chain test vehicles is described that includes correlation of alignment accuracy, CSAM and daisy chain electrical resistance. These test vehicles are compared to previous studies with pad sizes of 2 –10 μm.
The growth in demand for small form-factor and more capable electronic devices is driving a corresponding need for for advances in high-density interconnect technology to support high-speed, power efficient data transfer between chiplets or between systems-on-chip and memory. This paper presents, for the first time, electrical modeling and characterization results for $2-\mu \mathrm{m}$ line and space (L/S) and $1.5-\mu \mathrm{m}$ L/S signal wiring in high-density wiring layers in a panel-level organic interposer to address this need. The first part of this paper shows various high-density routing configurations $(< 5\mu\ \mathrm{m})$ formed in organic thin films, explicitly focusing on the effect on signal phase delays, crosstalk, insertion loss, and the range of characteristic impedance that fine line structures can provide; in this discussion, impedance matching to mitigate reflections is considered. To verify high-density signaling models, the second part of the paper focuses on electromagnetic simulations and hardware measurements taken at frequencies up to 20 GHz for 5.9-mm and 1.3-mm single-ended transmission lines. In addition to the agreement between measurement and simulation results for both $2-\mu \mathrm{m}$ and $1.5-\mu \mathrm{m}$ L/S configurations up to 20 GHz, this paper quantifies measured per-unit-length insertion loss of the high density wires at multiple frequencies to serve as a standard of comparison.
With the popularization of wide band-gap power modules in offshore wind power systems and water surface photovoltaic power stations, packaging materials face challenges of corrosion by salt, blended with high humidity. Copper-silver (Cu-Ag) composite sintered paste was proposed by researchers as a novel die-attach material for a lower cost and anti-electro migration ability. However, the potential difference between copper and silver forms galvanic corrosion in a high-humidity environment, resulting in accelerated failure combined with salt mist. To further promote the application of composite sintered materials, a copper-silver double-sphere galvanic corrosion model based on finite element simulation was proposed in this paper. The relationship between corrosion rate and time of different Cu-Ag particle size combinations under different sintering degrees was predicted by initial exchange current density. Through the electrochemical characterization of the sintered samples, the optimal combination of materials was further discussed. The accuracy of the model was also verified. The conclusions obtained from both the experiments and simulation work provide guidance for future anti-corrosion analysis, as well as the reliability improvement of novel composite sintered materials.
Transient-liquid-phase (TLP) Cu-Sn bonding is an attractive method for fabrication of intra-chip connects in 3-D and chiplet applications due to the ease of manufacturing and low cost. With the continuous increase in the interconnect densities, it is highly desired to shrink the Cu-Sn bump diameters to $\mathbf{5}\ \boldsymbol{\mu} \mathbf{m}$ or less from the current mainstream $\mathbf{20}\sim \mathbf{30}\ \boldsymbol{\mu} \mathbf{m}$ . However, small Cu-Sn bumps shows significant difference from large ones because some surface related properties that are insignificant for large bumps become dominant for small ones. This paper reports the differences between bonding of large and small Cu-Sn bumps, such as surface oxidation and bump undercut, and proposes the methods to address these problems. By optimizing the bonding processes, TLP bonding of Cu-Sn bumps with a $\mathbf{5}\ \boldsymbol{\mu} \mathbf{m}$ diameter has been successfully achieved.
The demand for higher thermal performance package increases and this is exacerbated by the increased of die and packages sizes. The insufficient coverage, interfacial separations, voids, and thicker Bond Line Thickness (BLT) of Thermal Interface Material (TIM1) caused by package materials and assembly processes prevent good thermal performance. Thermal impedance better than 15 mm2-C/W is needed for high-power applications. Lower thermal impedance is better for thermal performance. This work evaluated next generation TIM1s with thermal conductivity ranging from 4 to 10 W/m-K, the assembly of these materials with different lid attach processes and their reliability. It allowed Marvell and its OSATs to select the TIM1 that meets the thermal requirement of large die & package.
