In this paper process simulation of a novel structural Silicon On Insulator(SOI) LDMOS cell with Trench Gate and Field Plate and Trench Drain (TGFPTD) was done in a sequence of advanced SOI CMOS processes with Silvaco TCAD. The simulated results indicate that the proposed TGFPTD SOI LDMOS cell is feasible to be fabricated in advanced SOI CMOS technologies and the vertical channel length of the vertical gate nMOSFET can be reduced to about 130 nm.
A hydrogel actuated microsystem employed in controlling the opening-closing states of a microvalve is described. This microsystem consists of a flexible silicone rubber diaphragm with an attached silicon boss and a cantilever beam. Swelling of the hydrogel forces the bossed membrane and consequently the cantilever beam to be deflected. Simulations were done by FEM analysis and the results show enough deflections to open the valve and let the fluid flow through the microvalve.
Research on microneedles has been increasing rapidly to overcome the drawbacks of hypodermic needle which can results in painful injection, tissue damage and uncontrollable delivery rate. This paper presents process characterization of wet isotropic etching for solid microneedles array development. Work has been carried out to investigate the isotropic etching behavior in 17 different compositions of HNA solution. The experimental responses of vertical etch rate and lateral etch rate are presented. Resulting surface profiles from various HNA compositions are also reported. The etching properties will be applied to develop recipe to fabricate the optimum solid microneedles.
This paper reports the fabrication of a quantum dots (QD)-organics hybrids light-emitting diode (LED) for potential light sources. Organic light emitting diode (OLED) have become a focus of attention since past decades for potential light sources in a flat panel displays applications. Despite their intriguing performance in producing rich-color light emission, they still faced several critical defects, such as relatively low-brightness, low-chemical and photostability and short lifetime. Here, we demonstrate a novel system for the production of pure-color light emission with exceptionally high brightness by utilizing quantum dots that are hybridizing with light emitting organic materials, as an active material in light - emitting diode devices. Organic-quantum dots hybrid LED devices was fabricated by sandwiching the quantum dots monolayer between the electron transport layer (ETL) and hole transport layer (HTL) in a conventional OLED structure (ITO/ETL/QD/HTL/Al). Quantum dots of CdSe (ZnS) core-shell structure were function as the emitting layer. The ETL and HTL were poly(vinyl carbazol), PVK and tris(8-quinolinolato)aluminum(III), Alq3; respectively. The current-voltage (I-V) characterization on the device was found that the hybrid LED exhibited a strong blue emission under a relatively low bias voltage, of which their turn-on voltage was as low as 5.0 V.
SAMEER has recently setup an infrastructure to 'Pigtail and package Laser diodes' using optical epoxy and laser weld techniques. Few Laser diodes have been packaged using 'Fiber Alignment and Laser Weld System (FALWS)' in Butterfly and TO-CAN packages. The high power laser diode packaging involves good thermal management and post-weld shift challenges, and it is being experimentally verified with theoretical simulation. The Laser Diode packaging followed by reliability test as per Telcordia standard is the current technical challenges ahead.
Measurement of the foot and shoe interface pressure underpins a number of important applications. Abnormal pressure may indicate instability in gait, risks of diabetic ulceration and many other biomedical and sports applications. As the current foot pressure sensors in the market exhibit many limitations, a new sensor design based on the more promising MEMS technology was therefore explored. As such, this paper reports the analysis and optimization of a MEMS pressure sensor for foot pressure measurement. The pressure sensor had a high linearity output with pressure span of more than 2-MPa. This characteristic indicates excellent potential for a wide spectrum of biomechanical activities.
Electrical overstress has historically been one of the leading failure damage of integrated circuit. The result of an EOS event can range from soft damage with degradation to the IC up to catastrophic failure where the IC is permanently non-functional. Recent development of new DRAM technology with shrinking gate oxide dimension revealed severity of EOS failure mechanisms increasing obviously and proved to be a challenge to traditional failures analysis technique. Various analytical techniques have been introduced for EOS localization finding. In this paper, a non -destructive technique (X-ray and ultrasonic wave scanning) has been applied for component failure analysis.
In this paper, a 40 V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both the critical layout dimensions and implantation scheme. The optimized condition from DOE model provides good breakdown voltage with low Rdson, the values are BVDSS ~77 V & ~59 V; Rdson mu 84 mOmegamm2 & mu192 mOmegamm2 for n-LDMOS p-LDMOS respectively. Final tuning of the process & layout done by splits to improve the other device parameters such as leakage current, substrate current for better reliability & etc.
The integration of semiconductor electronics and diverse optics with miniature MEMS fluidic systems has produced remarkable capabilities, which have spawned a new industry, primarily in the past decade. Microfluidics devices made by several companies, most of them start-ups, enable point-of-care analyses for clinical samples and on-site field studies, as well as instruments for research and development. The companies, the materials and processes they use to make devices, the techniques employed for detection, and the markets are the subjects of this overview of the microfluidics industry.
The continuing scaling down of CMOS technologies contributes to the important of having early circuit simulations even before any real silicon data are available. This paper presents a methodology to extract a pre-silicon MOSFET mismatch model using backward propagation of variance (BPV) technique. All the required steps such as the correlation of process and electrical parameters through BSIM3v3 SPICE model and explanation of mathematical relationships among the parameters are discussed. The experimental data for mismatch analysis are projected from 0.35 um process to 0.25 um and 0.18 um processes using the technology scaling coefficient coupled with the related statistical data analysis. The good agreement between experimental and Monte Carlo SPICE simulation data verifies the proposed extraction methodology.
A low voltage, low noise instrumentation amplifier (IA) applicable for Electrocardiogram signal acquisition system has been designed. The circuit is based on the current feedback topology which has been implemented using folded cascode structure at the input stage. It works at zero input common mode voltage with 1V supply. It has a wide input dynamic range of plusmn0.01 mV to plusmn1.2 mV. The voltage gain is 45 dB and it consumes 165 muW power. A high common mode rejection ratio (CMRR) of 125 dB has been achieved. The integrated input referred noise is 3 muV rms (0.2Hz - 150 Hz). The design has been done in 0.18 mum standard CMOS process.
In this paper the response of printed thick-film of WO3 doped by Y2O3 to organic solvent was studied. Different ratio of doping was prepared and changes of film resistance at different temperature in present of vaporized types of alcohol were observed. The results showed a high sensitivity of the film of 80.1%WO3-18.8%Y2O3 to Toluene, Xylene, Methanol, and 2-Propanone (Acetone) at 250, 450, and 550degC, and higher sensitivity of 94.3%WO3-4.7%Y2O3 at 350degC. Microscopic images of the samples including SEM and TEM were observed. EDX and XRD analysis onto the samples also were done.
Summary form only given. As integrated circuit (IC) technology continues the trend towards sub-45 nanometer feature sizes, it is imperative to retain performance of back-end features such as on-chip interconnects while gaining the cost benefit of scaling. Some major barriers to achieving continuous downward scaling include high resistance and questionable reliability of nanoscale copper lines, and power dissipation in densely packed integrated circuits. This work presents fundamental electrical and thermal characterization of carbon nanofibers (CNF) as a possible solution for next-generation back-end integrated circuit processing. Results of temperature-dependent electrical resistance measurements for CNF arrays demonstrate distinct metallic behavior of these novel nanoscale devices. The current capacity of CNF interconnect test structures is examined and the results are compared with an electrothermal transport model. The use of CNF/copper composite material as a thermal interface for IC packaging is explored and fundamental thermal resistance measurement results show promise of such a composite material for thermal management applications.
Unlike SRAMs, the access time of 3T1D DRAMs increase as the feature size becomes smaller. To combat this slow down, it has been suggested that the sizes of read related transistors be increased, a technique that has never been thoroughly explored. This paper deals with the exploration of the effects of the said technique, focusing on its effectiveness as a function of the width increase and how it holds up as feature sizes get smaller. Our results show that applying such technique sometimes has unexpected and surprising effects, including deviating the access time curve from its expected shape, and worse, even slowing the memory cell down even further at certain times-of-read. We also discovered that the effectiveness of the technique actually becomes more and more limited as feature sizes get smaller. At a smaller feature size, it would no longer be sufficient by itself, and would have to be combined with another technique to speed up the memory cell.
The effect of concentration, temperature and processing time in RCA cleaning that affect gate oxide quality are studied. This paper shows how these variables of pre-clean chemistry on the characteristic of silicon oxide as insulator material. The results indicate that gate oxide strength had correlation with RCA concentration and processing time, and, is least related to temperature.
This paper presents the merits and demerits of incorporating deep n-well (DNW) implantation NMOS structures in a forward-biased RF-Low Noise Amplifier (LNA). Two versions of a fully-integrated 2.45 GHz LNA design with forward-biasing are presented, a standard transistor version and a DNW transistor version, to evaluate potential improvements or possible degradation in performance by using a DNW structure. The RF performance characteristics of the standard LNA version are compared to the performance of the DNW LNA version. Simulation results had shown that the performance of the power gain and noise figure has been significantly boosted through the use of the DNW transistor structure as amplifying devices.
Application of asymmetric sidewall vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the parasitic overlap capacitance in the asymmetric sidewalls vertical MOSFETs by using SOI (silicon on insulator) in bottom planar surfaces side. The result shows that while channel length decreases, the threshold voltage goes lower, the DIBL rises and subthreshold swing tends to decrease, for both structures. It is noted that the SVS MOSFET structure generally have better performance in SCE control compared to bulk vertical MOSFET. The presence of buried oxide is believed to increase the performance of vertical MOSFET, essentially in controlling the depletion in subthreshold voltage.
A thermo-optic multimode interference (MMI) switch with a ridge structure on top of the MMI and also introducing another ridge in the silicon substrate was proposed and the performance of the switch was simulated. In the design, one heating electrode is used to alert the refractive index at spot image which change the phase of this image to realize the switching function. The simulation results indicate that the MMI switch can satisfy 39dB crosstalk at two states. The electric power consumption for the MMI switch with these ridges is less than half of that of a conventional MMI switch.
In this paper, the first resonance frequency of the clamped square diaphragm of the capacitive acoustic sensor has been calculated using variational iteration method (VIM). The equivalent electrical circuit model using lumped parameters has been used to obtain the sensitivity of the sensor. The aim is to develop the microphones with high sensitivity and flat frequency response in hearing range. The high sensitivity can be obtained by changing the initial stress of diaphragm, sigma r , diaphragm size, a, diaphragm thickness, t, back plate thickness, h, air gap thickness, d, back plate hole radius, r, surface area fraction occupied by the holes, a., and bias voltage. The optimized structure has a diaphragm thickness of 0.8 mum, a diaphragm area of 2.43 mm 2 , an air gap of 4.0 mum and a 1.0 mum thick back plate with acoustical ports. The device shows maximum sensitivity 47.9mV/Pa, with a high frequency response extending to 18 kHz.
