The convex corner compensation methodes to manufacture diaphragms with V-grooves of semiconductor pressure sensors have been widely introduced. However, these methods do not seem to be efficiently used to manufacture very thin diaphragms with square masses. In order to make thin silicon diaphragms with different thicknesses where stresses are compensated, the convex corner compensation method to preserve square shaped convex corners should be established. In this paper, we have designed convex corner compensation patterns to make diaphragms of V-groove structures with mass and proved the superiority of this method by reasonable analysis.
A multi-level DAC with high intrinsic linearity and low power consumption enables a greater design space for wide-band continuous-time (CT) Delta-Sigma modulators (DSMs). This manuscript introduces an intrinsically highly linear 5-level switched-capacitor (SC) DAC with a power-saving charge recycling technique for wideband CT DSMs. We also adopt a distinct modulator architecture that places a large low-pass filter (LPF) capacitor at the input of the first amplifier. This architecture substantially enhances the modulator’s power efficiency and restores the modulator’s alias rejection ratio (AR) in the presence of an SC type of DAC. To validate the proposed techniques, a DSM prototype with a 10-MHz bandwidth and 800 MHz sampling rate (fs) is fabricated in a 65-nm CMOS technology. Consuming 1.3 mW from a 1.2-V supply, the prototype achieves a peak signal-to-noise-plus-distortion ratio of 72.3 dB and a dynamic range of 73.3 dB in experiments. The corresponding Warden’s and Schreier’s figures of merits are 19.3 fJ/conv-step and 171.2 dB, respectively. The measured ARs are 52.7 dB and 54.3 dB at fs and 2fs, respectively. The DSM further tolerates an rms clock jitter of 11 ps.
Multi-finger gate structure has been extensively applied to layout MOS transistors in RF analog circuits. The main advantage of this method is that a large drain current can be obtained with a compact silicon area. Furthermore, because of the reduced gate resistance, the cut-off frequency obtained from the multi-finger layout MOS transistor is higher than that of a single-finger transistor. This work will provide an empirical study on the impact of multi-finger layout on cut-off frequency for nanometer MOS transistors. It is shown that increasing the number of fingers in multi-finger layout has diminishing returns, and there exists an optimal number of fingers to achieve the highest cut-off frequency, and hence the RF performance of the transistor.
An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.
650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (Ron,sp) of 2.06 mΩ · cm2 (further reducible through tighter layout design) while having a narrow JFET region for device reliability.
This letter presents an implementation of a li-ion battery protector circuit making use of purely digital logic and resistive divider only, which results in a compact and energy efficient circuit. The presented design is capable to provide all protections, that is compatible with other commercially available li-ion battery protectors. In particular, a reset clock has been implemented to reset the protector circuit periodically when it enters into one of the hazardous protection state, which serves as an auto-recovery function to restore the battery protector to normal operation without external assistance. Finally, the reset clock can be overridden with an external test clock which helps to reduce the test time of the integrated circuit in wafer level during mass production. The performance of the proposed circuit is validated by implementing the circuit on FPGA with external resistors, which further confirms that the fabrication of the proposed circuit on silicon is feasible.
In this paper, we report the Fe doped MoS2 monolayer to improve the gas sensing properties. We investigated the electronic properties of Fe doped MoS2 for sensing Urea and Methanol using Density Functional Theory (DFT). Non-Equilibrium Green's Function (NEGF) was used to calculate the transport properties of the aforementioned nanomaterials. The absorption energy, charge transfer, bandstructure, Density of States (DOS), Projected Density of States (PDOS), I-V characteristics, recovery time and sensitivity of urea and methanol gas molecules on Fe doped MoS2 were all investigated. As a result, we observed the tremendous change in the electrical and chemical activity of Fe doped MoS2 for the adsorption of urea and methanol. After the substitution of the Fe atom in the MoS2 monolayer, the magnetic property was observed. In comparison to pristine MoS2 and Fe doped MoS2, the bandgap revealed an improvement in conduction property in adsorbed molecules. The outcome was also confirmed by DOS and PDOS. The Fe doped MoS2 for urea and methanol adsorption, the I-V curve shows a linear increase in current for bias voltage up to 1.9 V, then a quick fall in current after increasing a few volts. The relative resistance state of the Fe doped MoS2 based sensor is better, indicating that it can be used as a sensor. At 2 V, the sensitivity for methanol and urea was 82 % and 77.5 %, respectively. For the methanol configuration, the quicker desorption time was calculated to be 0.00015 µs. Our results demonstrate that Fe doped MoS2 is a promising candidate for a low-cost, stable gas sensor.
In this manuscript, a novel 2nd-order noise-shaping successive-approximation register (NS-SAR) analog-to-digital converter (ADC) is introduced for potential application in wideband continuous-time (CT) ΔΣ modulators. The proposed NS-SAR employs a special active-passive residue filter that reuses the capacitor of the reference digital-to-analogue converter (DAC) of the SAR. Compared to the conventional NS-SAR that uses an active residue filter, the proposed approach saves one power-hungry amplifier and four replica DACs. An asynchronous 2b/cycle conversion scheme is adopted for a reduced excessive loop delay (ELD) in the modulator. Transistor-level simulations in a 65nm CMOS process are presented to demonstrate the principle of the proposed NS-SAR.
In this work, a double gate junction-less tunnel FET (DG-JLTFET) has been evaluated for biosensing applications. Tunnelling is the concept in JLTFET which is a heavily doped JL transistor, by decreasing the barrier length between the source and channel of the device which is easily used for switching (ON and OFF) purpose. Based on the research and simulation so far on JLTFET, this has achieved a greater performance when compared to that of MOSFET. JLTFET with more dielectric (k) and low K spacers will give an ON current (0.1 mA/µm) for gate voltage 3V and for off current of (10−15 A/ µm) and performance with Ion/Ioff ratio at 1012 and subthreshold swing with 60 mV/dec is obtained at 20 nm length of the gate at room temperature. So, JLTFET is a better device for switching performance. The evaluation of device performance is also done based on different cavity thicknesses and different dielectric constants. Including these parameters, double gate-pocket-junction-less TFET is highly used in biosensor applications. In the following, we demonstrate high performance based on pocket region which is introduced to implement in JLTFET for biosensor label-free detection
A low power current comparison based voltage detector with on-chip detection voltage trimming is proposed in this paper. The proposed trimming technique achieves both detection voltage trimming and detection voltage accuracy trimming. The performance of the proposed circuit is validated by simulation using a 0.5 μm CMOS process. A short power-on rising time (trise) of less than 1 ms can be achieved due to the utilization of current comparison technique. Trimming accuracy on the detection voltage at ±1.875% is obtained. The proposed circuit consumes 140 μW at supply voltage of 5 V. The overall active silicon area of the proposed circuit is 27900 μm2, which is comparable with that of other reported circuits without trimming functions. The proposed circuit is suitable for the application in a variety of power management application where energy efficiency is a consideration.
It is expensive if not impossible to fabricate embedded resistors to the correct resistance value. Therefore, embedded resistor is often fabricated with a typical value and then use a post-fabrication trimming process to trim it to the desired value. This tutorial discusses how to set up the resistor network appropriately to achieve the desired resistance through trimming. The trimming strategy is studied analytically, with a number of variations in the trimming topologies. A voltage reference circuit is applied as the underneath application in this tutorial such as to provide more concrete discussions on the physical meaning of trimming accuracy.
This article presents a tutorial on the design of CMOS Class AB bridged audio amplifier. High power efficiency is achieved by using a bridged output stage. An added advantage of the bridged amplifier is that the output stage can operate without the use of any capacitor, which supports the circuit to be operated under single rail power supply. An example of 3 WRMS audio amplifier with 3Ω load is presented in this tutorial together with detail analytical analysis to demonstrate how to design a similar CMOS audio amplifier. The design example is simulated with a commercial 0.5 μm CMOS process together with measurement results from fabricated silicon to sustain the presented design methodology. The fabricated amplifiers can achieve low quiescent power at 33 mW, and a wide peak-to-peak output voltage swing of 8.5 Vpp subject to a 5 V supply. The THD of the amplifier is measured to be smaller than 10%.
A novel classification technique is applied for identifying carbon nanotube FET and quantum wire FET based on their electrical characteristics and percentage error is estimated using multi-layer perceptron analysis to justify the accuracy of computation. Two different cross-validation methods, namely decision table and multilayer perceptron (MLP) are applied on same data set of both the devices, and results speak about higher accuracy when MLP is performed. Also, for different testing-training set of data, MLP performs far better than conventional decision table approach; when correlation coefficient, mean absolute error, root mean squared error, relative absolute error and root relative squared error are computed. For comparative study, similar geometrical configuration, and equivalent biasing arrangement of both the devices are assumed, and identical number of iterations is performed for equal subsets. Results speak supremacy of MLP technique applied for classification and identification of nanometric devices based on their electronic attributes.
A double edge-triggered D-type flip flop includes a half-static clock gating circuit is presented in this paper. Two dynamic latches that each responses to the rising and falling edges of the gated clock are connected in parallel to a half-static latch, which captures the data signal in response to both rising and falling edges of the clock signal. This flip flop topology helps to improve the race tolerance, energy efficiency and circuit compactness. The flip flop is simulated with HSPICE using commercially 0.18 µm CMOS technology. The simulation results presented in this paper showed that it can achieve a 4 Gbits/sec data rate with 96% redundant power reduction when compared to other double edge-triggered D-type flip flop in literature.
In this paper, a 5-bit 500MS/s flash analog-to-digital converter (ADC) with temperature-compensated inverter-based comparators is proposed. In the proposed ADC, a complementary-average system structure is adopted. Based on this structure, inverter-based comparators are used to reduce the power consumption. However, conventional inverter-based comparators suffer from switching threshold variation when the temperature changes, which degrades the SNDR performance of the whole ADC. To tackle this problem, a temperature-compensated inverter-based comparator is proposed. Furthermore, an encoder with majority-3 bubble error correction is used in the proposed ADC to reduce bubble errors. To verify the proposed design, a prototype ADC is implemented in a 0.18 µm process. Measurements at room temperature show that the SNDR and SFDR of the proposed prototype are 29.6 dB and 34.92 dB, with a resulting ENOB of 4.62 bits. It achieves an DNL and INL of +0.33 LSB /−0.54 LSB and +0.27 LSB/−0.33 LSB, respectively, and consumes 6 mW from a 1.8-V supply. At 0 °C and 60 °C, the ADC maintains a close performance.
This letter describes the design optimization of a flash memory cell that uses source-induced band-to-band hot electron (SIBE) injection programming method. The programming efficiency is determined by the tunneling current to the floating gate, which is shown to be dependent with the gate length covered width. Optimal gate length covered width is empirically studied in this work through simulation, and we are able to observe more than an order of magnitude increase in the programming efficiency which tremendously reducing the total power consumption of the flash memory.
An improved design procedure for double balanced Gilbert cell mixer is proposed for specific gain and power requirements at various license exempted frequency ranges for a variety of wireless equipment in India. The down conversion mixer design is aimed to carry out in 130 nm CMOS process. At 2.5 mW d.c power, a conversion gain of over 10 dB and a noise figure under 10 dB is intended at minimum overdrives for transconductance and switching stages of the mixer. Several optimization techniques for enhancement of gain, linearity and noise performances of the designed mixer are presented. An improvement in linearity about 10 dBm is targeted for 1-dB gain compression as well as third order intercept points introducing a unique criterion to integrate and exhaustively explore the enhancement techniques while preserving the gain as well as noise performance of the mixer.
A new 3D finite element model to characterize the residual stress distribution in multilayer NTC thermistor during soldering process has been developed. During the soldering process, the effects of inner silver electrode number and lateral margin length on mechanical residual stress are studied. Throughout the weldbonding and heating process, the maximum and minimum principal stresses in the active region of the thermistor ceramic are not zero, which implies that most of the thermistor ceramic is not stress-free. Numerical results show that the increasing of the lateral margin length could effectively decrese the maximum tensile stress.
The current-voltage (ID-VD) characteristics of W/4H-SiC Schottky barrier diodes (SBDs) are investigated in the 303–448 K temperature range by means of a numerical simulation study. Results showed a good agreement with measurements for a bias current ranging from 100 nA up to 10 mA. The main device parameters, such as the barrier height and ideality factor are found strongly temperature-dependent. The observed behaviours are interpreted by using the thermionic emission (TE) theory with a single Gaussian distribution of the barrier height (BH). The corresponding Richardson constant is A* = 148.8 Acm−2K−2. This value is close to the theoretical one of 146 Acm−2K−2 for n-type 4H-SiC.
In this work, the impact of back gate work function on analog/RF performance of Asymmetric Junctionless Dual Material Double Gate MOSFET with high K gate Stack (AJDMDG Stack MOSFET) has been studied. The impact of back gate work function on analog/RF parameters like drain current (ID), transconductance (gm), transconductance generation factor (TGF), intrinsic gain, output resistance (rout), cut-off frequency, maximum frequency of oscillation (fmax) etc. have been studied through TCAD device simulator. The results reveal that an improvement in analog/RF performance has been achieved by choosing a low value work function of the back gate.
