The convex corner compensation methodes to manufacture diaphragms with V-grooves of semiconductor pressure sensors have been widely introduced. However, these methods do not seem to be efficiently used to manufacture very thin diaphragms with square masses. In order to make thin silicon diaphragms with different thicknesses where stresses are compensated, the convex corner compensation method to preserve square shaped convex corners should be established. In this paper, we have designed convex corner compensation patterns to make diaphragms of V-groove structures with mass and proved the superiority of this method by reasonable analysis.
A multi-level DAC with high intrinsic linearity and low power consumption enables a greater design space for wide-band continuous-time (CT) Delta-Sigma modulators (DSMs). This manuscript introduces an intrinsically highly linear 5-level switched-capacitor (SC) DAC with a power-saving charge recycling technique for wideband CT DSMs. We also adopt a distinct modulator architecture that places a large low-pass filter (LPF) capacitor at the input of the first amplifier. This architecture substantially enhances the modulator’s power efficiency and restores the modulator’s alias rejection ratio (AR) in the presence of an SC type of DAC. To validate the proposed techniques, a DSM prototype with a 10-MHz bandwidth and 800 MHz sampling rate (fs) is fabricated in a 65-nm CMOS technology. Consuming 1.3 mW from a 1.2-V supply, the prototype achieves a peak signal-to-noise-plus-distortion ratio of 72.3 dB and a dynamic range of 73.3 dB in experiments. The corresponding Warden’s and Schreier’s figures of merits are 19.3 fJ/conv-step and 171.2 dB, respectively. The measured ARs are 52.7 dB and 54.3 dB at fs and 2fs, respectively. The DSM further tolerates an rms clock jitter of 11 ps.
Multi-finger gate structure has been extensively applied to layout MOS transistors in RF analog circuits. The main advantage of this method is that a large drain current can be obtained with a compact silicon area. Furthermore, because of the reduced gate resistance, the cut-off frequency obtained from the multi-finger layout MOS transistor is higher than that of a single-finger transistor. This work will provide an empirical study on the impact of multi-finger layout on cut-off frequency for nanometer MOS transistors. It is shown that increasing the number of fingers in multi-finger layout has diminishing returns, and there exists an optimal number of fingers to achieve the highest cut-off frequency, and hence the RF performance of the transistor.
An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.
650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (Ron,sp) of 2.06 mΩ · cm2 (further reducible through tighter layout design) while having a narrow JFET region for device reliability.
