Modern low-power VLSI architectures face increasing energy challenges due to data-intensive workloads in IoT and edge-AI systems. A data-centric power modeling approach was developed to capture switching activity, memory hierarchy behaviour, and on-chip data movement, enabling accurate estimation of energy beyond compute-only analysis. To accelerate power-performance estimation across large architectural design spaces, a unified graph-based hardware representation and a Graph Neural Network (GNN) surrogate were built to predict Power, Performance, and Area (PPA) with sign-off-level accuracy while avoiding costly full EDA simulations.Building on this foundation, this work introduces a reinforcement-learning-driven multi-objective Design Space Exploration (DSE) framework that automatically identifies Paretooptimal VLSI configurations. The GNN surrogate provides rapid PPA evaluation, and uncertainty-based pruning eliminates low-value candidates, significantly reducing the number of PrimeTime-PX simulations. A non-dominated sorting mechanism extracts the final Pareto frontier while optimizing for minimum power, reduced latency, and area constraints. Experimental evaluation on CNN, RNN, FFT, and DNN workloads shows an average 32% reduction in total power, 35% lower energy per inference, 17% latency improvement, and up to 75% fewer full simulations.
In analog and mixed-signal circuit applications, the bandgap reference (BGR) circuit generates a reliable output. However, process, voltage, and temperature fluctuations all have an impact on output performance. Capacitors, resistors, and amplifiers increase the size of power supplies. As a result, the trimmer circuit is recommended for the BGR circuit to reduce fluctuations and process extension. Temperature compensation provides better temperature coefficients by adjusting the transistor voltage aspect ratio. The final characteristic curves are corrected to avoid slope variations, and temperature adjustment is required to provide the reference current in the BGR circuit. Temperature coefficients (TC) are calculated using electron mobility, voltage drop across the transistor, and threshold voltage factors. The temperature-dependent threshold voltage generates a low dependency drain current. Temperature reparation is achieved through temperature coefficients, and gate-source voltage is generated in the BGR circuit. Monte Carlo simulation beats efficient methods for identifying process variations and mismatches. Designing cascade current mirrors in the BGR circuit reduces the channel length modulation impact while increasing the resistance value. The trimmer current reference circuit outperforms the efficient reference current 21 & micro;A at time of 110 to 150 & micro;S .
In recent ICs, the use of sub-threshold power management has become a necessity due to energy-efficiency. Level Shifters (LSs) are used to exchange signals between different voltage domains. They ensure the reliability of ICs and signal integrity. The low-power LS shown is a combination of multi-Vt, diode connected leakage aware, load balancing design, allowing for up shift or down-shifts. In this article the Performance optimization of Super Scalar level Shifter for High performance Computing Applications (SSLS) is proposed. SSLS integrates multi-Vt, and load-balancing inverter for optimization of performance metrics. The schematic structure is capable of converting voltages high into low as well. It is the design architecture that has the least silicon area. The proposed design is implemented using 55 nm-CMOS. This LS is capable of converting voltages from 0.30 V to 1.30 V with a 2.01 nW dynamic power. The LS has a propagation area of 7.660 um 2 and a delay of 90 ps.
Flexible piezoresistive sensors are becoming increasingly popular for soft robotics, wearable electronics, and structural health monitoring because of their low processing costs, mechanical versatility, and light weight. Here, we present the creation and multiphysics simulation of a flexible piezoresistive sensor using screen-printed SWCNT ink on polymer substrates. To achieve controlled film thickness and good adhesion, the experimental work focuses on creating a uniform SWCNT(Single Walled Carbon Nanotube) ink and using a scalable screen-printing process to deposit it. In addition to fabrication, a COMSOL Multiphysics model was created to examine the printed sensor's electromechanical response to tensile loading. In order to investigate displacement, von Mises stress, relative resistance variation, and electric potential distribution, the model combines modules for solid mechanics and electric currents. Under 0-50% tensile strain, the screen-printed CNT resistors exhibited highly linear resistance-strain responses (R2 = 0.998 for PI, 0.961 for PVC, and 0.968 for OHP) with the corresponding gauge factors at epsilon = 0.50 were 2.60 (PI), 0.85 (PVC), and 1.89 (OHP), consistent with the lower-mid range reported for printed CNT composites. Consistent with experimental trends, the simulation results demonstrate a linear resistance variation with strain and high gauge factor values. The electric potential plots shed light on charge transport throughout the printed film, while the stress distribution emphasizes the stability of the SWCNT film-substrate interface.
Ensuring data integrity is a crucial aspect of secure communication among interconnected smart devices. These systems typically employ FPGA, ASIC, or embedded processors as their core computational units. Due to their design constraints, such platforms operate with limited memory, computational power, and energy resources. This study provides a comprehensive evaluation of various lightweight block (64/128 parallel and serial variants), RECTANGLE (80/128), Klein, and mCrypton implemented on resource-constrained FPGA-based IoT architectures. Among these, AES remains widely adopted due to its balanced performance, offering a data throughput of approximately 17.7 bytes/s and a key scheduling throughput of 35.5 bytes/s. Conversely, PRESENT, recognized as one of the earliest ultra-lightweight ciphers, demonstrates superior energy efficiency with a minimal on-chip power consumption of around 111 mW. The comparative analysis highlights the trade-offs between power efficiency, hardware utilization, and throughput across different lightweight cryptographic implementations.
