OpenVADL is an open source implementation of the Vienna Architecture Description Language (VADL). VADL is a processor description language (PDL) that enables the concise formal specification of processor architectures. OpenVADL automatically generates an assembler, an LLVM based compiler and a QEMU based instruction set simulator from a single VADL processor specification. Automatic generation of synthesizable specifications in a hardware description language is under development. VADL strictly separates the instruction set architecture (ISA) specification from the microarchitecture (MiA) specification. VADL’s MiA specification operates at a higher level of abstraction compared to existing PDLs. This article introduces OpenVADL, describes the generator techniques in detail and shows the performance of the generators in an empirical evaluation. The evaluation demonstrates the capabilities of OpenVADL and its efficiency. An OpenVADL generated instruction set simulator is up to 77
A Flash Translation Layer (FTL) hides the intrinsic flash properties of SSDs and provides a block interface to the host. FTLs completely embedded in the firmware of SSDs must therefore duplicate host functionality, such as the translation between logical and physical blocks performed by a file system, introducing performance unpredictability and increasing device cost. Zoned Namespace (ZNS) SSDs overcome these drawbacks by only implementing limited FTL functionality inside the SSD and by exposing a more flash-friendly interface to the host. However, moving away from the block interface means that the storage stack inside the host must be modified for ZNS devices. This requires considerable effort, which is one reason why F2FS is the only Linux file system with reliable ZNS support today. This paper discusses how the Linux storage stack can be extended to simplify the process of adapting file systems to ZNS devices. It then proposes the host-side Zoned Translation Layer (ZTL), which provides abstractions and functionalities required by many file systems to support ZNS devices. We demonstrate the feasibility of ZTL by providing the first EXT4 implementation for ZNS devices and by comparing our implementation of ZNS support for F2FS with the native ZNS support of F2FS.
In this paper, a new 2-bit error correcting (DEC) linear code is presented as a modification of a corresponding 2-bit error correcting (DEC) BCH code. Compared to an unchanged BCH code in GF(2^m) with 2· m check bits and a code length of 2^m-1 , the number of data bits can be increased by at least m+1 bits. The number of check bits only needs to be increased by 1. New columns and a single new row are added to the parity check matrix of the unchanged BCH code. The added columns are determined according to the columns of a parity check matrix of any 2-bit error correction code with only m check bits. The bits of the added row distinguish between the columns of the unchanged BCH code and the columns of the added columns. The proposed method is particularly interesting for longer code lengths. Decoding remains simple even with long code lengths, as the known algebraic methods for decoding BCH codes can be used for most of the bits. A small look-up table is only required for the relatively small number of bits added.
Fuzzy spatial relations are increasingly utilized in visual reasoning tasks, such as semantic annotation and object recognition. However, these tasks often rely on compute-intensive fuzzy morphological operators, leading to significant latency during relation evaluation. Addressing this challenge requires optimized implementations that are tailored to modern architectures. Previous works introduced the Reverse (R) and Parallel Reverse (PR) algorithms for Intel processors, leveraging OpenMP and SIMD intrinsics. In this work, we extend these contributions to embedded systems by targeting ARM-based processors and NVIDIA embedded GPUs. Specifically, we propose three architecture-specific implementations: PR64N, using 64-bit NEON SIMD instructions; PR128N, using 128-bit NEON instructions; and PRGPU, a GPU-optimized version based on CUDA. Our evaluation is conducted on the NVIDIA Jetson Orin Nano Super platform, an advanced ARM-based system-on-chip designed for low-power edge AI applications. The results demonstrate that our CPU implementations achieve near-peak performance by fully exploiting the platform's memory bandwidth. Meanwhile, the GPU implementation efficiently offloads fuzzy spatial relation evaluations, allowing the CPU to manage additional workloads. These findings underline the suitability of our methods for enabling visual reasoning tasks on resource-constrained embedded systems and contribute to the broader discussion on addressing heterogeneous architectures with tailored algorithms.
Self-Adaptive and Self-Organizing (SASO) systems aim to tackle the challenges of information technology's growing complexity. While various control patterns exist to coordinate such systems, this Ph.D. project takes a fully centralized perspective as its starting point. The focus lies on developing a Central Control Unit (CCU) capable of multi-objective, self-aware optimization while balancing potentially conflicting local decisions. As part of the InHOSaS project, this research, along with a second Ph.D. project, will ultimately integrate the CCU with autonomous decision-making at the subsystem level, forming a hybrid approach. These methods are exemplified using the platooning use case, demonstrating the coordination of semi-automated or automated vehicles within the SASO framework to maintain both individual subsystem goals and overarching system constraints.
In the context of the Message Passing Interface (MPI), most implementations employ one of the following three mechanisms to ensure strong communication progress: using a background thread, dedicating a hardware core, or relying on the application to make frequent MPI test calls, such as MPI_Test, MPI_Testany, MPI_Testall, etc.. These mechanisms continuously ensure progress in communication operations by processing pending tasks, updating completion queues, and handling necessary callback functions, resulting in effective computation and communication overlap. However, these methods may lead to hardware resource consumption, which could otherwise be used for computation, while also increasing context switches between the main thread and the asynchronous progress thread. In this paper, we leverage the ARM cores integrated within NVIDIA’s InfiniBand BlueField Data Processing Unit (DPU) to offload the communication progress in non-blocking two-sided communication. This approach is implemented using Unified Communication X (UCX), leveraging the Unified Communication Protocols (UCP) API. Compared to Open MPI and MPICH, our results indicate that this approach significantly improves the overlap between communication and computation in scenarios with multiple non-blocking send and receive requests, achieving close to 100
Organic Computing (OC) systems tend to incorporate a self-adaptation mechanism allowing them to learn from perceptions of their environment. The hereby used self-learning component is typically a variant of the XCS Classifier System (XCS). XCS is seen as the most researched Learning Classifier System (LCS) which are rule-based Machine Learning systems. LCSs evolve and train populations of classifiers, also called rules, represented as condition-action-evaluation mappings, forming their knowledge base. For their rules, XCS variants employ conditions covering the state space of an environment based on static assumptions about the geometry or structure of the state niches. We take a closer look at using neural networks as so-called neural rules and neural conditions that should be able to evolve to cover state niches of arbitrary structure. While neural rules are far from novel, we modernise the approach and seek to improve the application of neural conditions to Reinforcement Learning problems. XCSF using neural rules and neural conditions was applied to different multi-step Reinforcement Learning environments. Our reported experiments show that they outperform the previous variant of neural rules in all cases, including a traditional XCSF using hyperrectangles in almost all environments.
In the age of advanced technology and automation, self-organizing systems capable of adapting flexibly to diverse situations are becoming increasingly critical. Organic Computing (OC) addresses this challenge by drawing inspiration from biological processes to develop systems that respond autonomously and robustly to environmental changes. Within such systems, decision-making plays a pivotal role, with the XCS classifier system (XCS) emerging as a prominent method. Another category of algorithms that fits this requirement is reinforcement learning (RL). However, a comprehensive comparison of XCS and RL remains scarce. This paper bridges this gap by presenting an extensive empirical analysis of XCS and various RL algorithms across 51 problem instances from five established RL benchmarks of varying complexity. The results show that while XCS performs competitively on simpler problems, it fails completely on two of the benchmarks, making RL a more suitable alternative to XCS in selected OC systems. While XCS is robust in noisy environments, this trait is not unique. Other algorithms exhibit comparable stability and significantly outperform XCS in complex scenarios with larger state and action spaces.
In missions using autonomous underwater vehicles (AUVs), reaching predefined waypoints is essential, e.g., for seabed mapping and infrastructure monitoring. The primary objective is to minimize energy consumption to reduce the risk of failure, avoid long (re)charging times, or maximize the number of successfully visited waypoints. If the AUVs can visit the waypoints in any order, we can frame this as a Travelling Salesperson Problem (TSP). However, finding the global optimal solution to the TSP becomes computationally infeasible even for relatively small sets of waypoints. To address this challenge, we utilize Particle Swarm Optimization (PSO) as a lightweight alternative, allowing us to obtain energy-efficient routes that closely approximate the global solution. Choosing the corresponding hyperparameters is fundamental, as poor selections can lead to local optima. Our analysis shows significant differences in the sensitivity of hyperparameters between the two PSO-based approaches, which only differ in initialization. However, there is a consistent range of hyperparameters where both methods yield comparable results. We identify this range by optimizing hyperparameters to improve solution quality. Simulative evaluations in real-world-inspired scenarios demonstrate that optimized hyperparameter selection improves the energy efficiency of the AUV swarm and ensures reliable mission execution using a minimal number of AUVs.
Self-explainability is seen as an enabler for a broad acceptance of Organic Computing (OC) systems and the overarching field of self-adaptive and self-organising (SASO) systems within industry and society. Organic Traffic Control (OTC) is a system following the OC design principles to establish a self-adaptive and self-learning traffic management of intersection controllers in urban environments. Nevertheless, it is missing the self-explanation property. A step-by-step approach to self-explanation includes detecting the necessity for an explanation, then finding a cause for the observed behaviour, and finally translating the results in a good explanation for the different groups of users. We propose our research plan to utilise incident detection and classification to enable self-explainability in OTC. Additionally, we aim to generalise from our findings to enable self-explainability in multiple different SASO systems.
Memory is a central component in every computer system. Hardware evolution has led to greater capacities and higher speeds, but essential properties of its hardware/software interface have been unchanged for decades: Main memories used to be passive, largely homogeneous, and volatile. These properties are now so firmly anchored in the expectations of software developers that they manifest in their products. However, a wave of innovations is currently shattering these assumptions. In this sense, several new memory technologies are disruptive for the entire software industry. For example, new servers combine "high-bandwidth memory" with classic memory modules and CXL enables even more hybrid architectures (non-homogeneous). The "in-/near-memory" computing approaches abandon the Von Neumann architecture and promise huge performance improvements by allowing CPU-independent processing of data objects in or close to the memory (non-passive). Finally, "persistent memory" is available for servers and embedded systems (non-volatile). Overall, the expectations are high. Computers could have lower energy consumption, more performance, improved reliability, and reduced costs. However, from the (system) software perspective it is largely unclear how to use the novel memory technology efficiently. The DFG priority program 2377 addresses this problem. This overview discusses the state and potential of disruptive memory technologies, the challenges for system and application software, and important research directions.
In the field of intelligent transportation systems, accurately modelling cyclist behaviour is crucial to enhancing traffic safety and efficiency, particularly as road environments are increasingly shared with automated vehicles. Modelling cyclist behaviour is intrinsically complex due to its dynamic, context-dependent nature, shaped by diverse environmental and individual factors. These complexities pose significant challenges for traditional centralized learning approaches, particularly regarding data privacy concerns and heterogeneity across distributed data sources. Federated Learning (FL), as an emerging framework, offers the potential to address these challenges by enabling collaborative model training without sharing raw data. However, in real-world traffic scenarios, FL must tackle the complexities of non-independent and identically distributed data and the need for real-time adaptability in dynamic traffic environments. This work explores an uncertainty-aware FL framework, incorporating multimodal data fusion, to support modelling cyclist behaviour in traffic environments. This research addresses key challenges in FL for cyclist behaviour modelling and explores potential solutions, offering both theoretical and practical insights for future applications in intelligent transportation systems.
Computer systems are prone to crashes and power outages, particularly in intermittent computing scenarios where embedded systems rely on unreliable energy-harvesting sources. Hybrid caches, which integrate volatile and non-volatile memory (NVM) sections, offer opportunities for efficient operating system (OS) services to ensure data persistence over power interruptions. However, the lack of OS awareness of hybrid cache structures can result in inefficient backups, data loss and inconsistencies, as well as underutilization of the potential of hybrid caches. This paper introduces the Cache Hybridization-aware Operating System (CHaOS), that is based on a co-design of the OS and the underlying hardware to systematically persist volatile states and data in case of power outages. Our evaluation demonstrates that CHaOS not only proves robust against power outages, but also can significantly reduce the backup latency. In our test of using CHaOS to execute an image processing application on a hybrid-cache system, already with 75
Semi-structured data formats, such as JSON, are widely adopted in big data applications to achieve flexibility, fast integration and portability. As these formats are commonly highly sparse, compression is often applied before data is stored or transmitted over networks. However, since semi-structured records often need to be accessed individually, they need to be compressed separately, resulting in low compression factors when applying traditional Lempel-Ziv compression schemes. As a remedy, Fast Static Symbol Table (FSST) was proposed, a lightweight dictionary-based compression scheme specifically designed for short strings. In this paper, we present hardware acceleration techniques for the FSST compression scheme. Moreover, we evaluate the applicability of FSST to semi-structured data, such as JSON, and compare it to other compression schemes. Finally, in the evaluation of the presented accelerator circuits, we report speedups of 1.4 to 2.6 times and a reduction in energy consumption of 6.0 to 10.5 times compared to the open source FSST software implementation.
Organic Computing (OC) systems adapt to changes in the system or environment to maintain system performance. Therefore, those systems integrate a control part, which can be implemented centralized (globally) or decentralized (locally)-mixed (hybrid) approaches are feasible. When determining the performance of such a system, various metrics can be observed, which generally cluster in system-specific and adaptation metrics. Whereas the first category is domain-specific and measures the system's performance, the second measures the adaptation performance and can be used system-independently for evaluating OC systems. In this paper, we present a measurement framework that takes into account this split in quality attributes. We show how to apply the measurement framework in a hybrid OC system based on the example of platooning coordination.
Cache memory is a critical resource for performance, and as is well known, faults in it can significantly impact processor efficiency. In our everyday life, in non-critical real-time applications, it is desirable for quality of service that performance remains high, and that the worst-case execution time is as close to the average as possible. In this paper, we demonstrate that neither disabling only the faulty cache sub-blocks [1] nor disabling entire blocks that contain at least one faulty sub-block [23] yields optimal results in terms of average performance and performance variance in faulty CPU caches. Instead, we show that selectively disabling blocks with more than N faulty sub-blocks, while disabling only the faulty sub-blocks in all other blocks, leads to better average performance and lower performance variance. The optimal value of N depends on both the fault percentage and the granularity of the sub-block.
The research alliance "FORnanoSatellites - Innovations in nano-satellites - Advanced assembly and mounting technology (AMT), packaging, computing technology, and applications", funded by the Bavarian Research Foundation, pursues the design a new generation of nano-satellites, which have a spatial dimension of a few dm(3) and mass of only a few kilograms. In the 'New Space' sector, nano-satellites are already opening up a wide range of applications in telecommunications, earth observation, and navigation in a cost-effective manner, e.g. in multisatellite networks. Standardization approaches are intended to support a cost-efficient production of hundreds of satellites. FORnanoSatellites intends to carry out research work to boost the development of small-scale production of nano-satellites in the long term. Open research challenges are in (i) the area of computer architecture for processing data. Furthermore, for the success of this technology (ii) a new mounting and interconnection 3D stacking technology of all components is required and a web configurator is foreseen to support the design of nano-satellites. To ensure reliable operation under harsh space conditions, (iii) appropriate redundancy concepts must be considered in hardware and software. Furthermore, we a (iv) new optical communication in nano-satellites and a new concept for a satellite bus is aspired. As already discussed at NASA and ESA for larger satellites, the computer architecture should also open up RISC-V and FPGA processor technology for nano-satellites.
Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration.
With the growing demand for artificial intelligence and other data-intensive applications, the demand for graphics processing units (GPUs) has also increased. Even though there are many approaches on multiplexing GPUs, none of the approaches known to us enable the operating system to coherently integrate GPU resources alongside CPU resources into a holistic resource management. Due to the history of GPUs, GPU drivers are still a large, isolated part within the driver stack of operating systems. This paper aims to conduct a case study on how a multiplexing solution for GPGPUs could look like, where the OS is able to define scheduling policies for GPGPU tasks and manage GPU memory. We will discuss the architecture of MxGPU, which offers software-based multiplexing of integrated Intel GPUs. MxGPU has a tiny code base, which is a precondition for formal verification approaches and usage in safety-critical environments. Experiments with our prototype show that MxGPU can grant the operating system control over GPU resources while allowing more GPU sessions with less overhead compared to existing work.
This paper addresses the challenge of unsupervised anomaly detection in key metrics related to data transmission in fourth and fifth-generation (4G and 5G) cellular networks, with the main aim of developing a monitoring service that can alert on abnormal behavior in real-time. The dataset used in this research includes channel and upper-layer performance metrics collected from several cellular modems deployed on a remote-controlled ship. Deep autoencoders (DAE) were selected as the main approach due to their ability to detect point, contextual, and collective anomalies. Several unsupervised machine learning algorithms and preprocessing techniques were applied and optimized to overcome the problem of using DAEs for unsupervised anomaly detection, namely their need for training data containing no known anomalies. Different types of deep autoencoders, including classical, variational, denoising, and robust models, as well as different neural network architectures, consisting of linear and recurrent layers, along with the additional loss function terms, such as contractive and sparse regularizations, have been explored. The presented approach is evaluated using anomalies generated by unsupervised algorithms and special samples that introduce noise and shuffling into normal data, thus affecting the data distribution. Finally, a post-analysis is performed by adding contextual information to the data to help interpret the detected anomalies introducing another layer of validation to the presented approach.
