Embedded system applications normally come with a set of nonfunctional requirements on execution properties (e.g., latency), expressed by a corridor of permissible values. These requirements should be guaranteed during each program execution on a given MPSoC platform. This can be achieved using a reactive control loop based on a requirement response, with an enforcer finite state machine (FSM) controlling the properties to be enforced, e.g., by adapting the number of cores allocated to a program or by scaling the voltage/frequency mode of active processors. A finer-grained control can be achieved using response ranges, which allow an enforcer to react based on the amount of violation of a requirement. But as the search space of enforcer FSMs to be explored by design space exploration (DSE) can be quite huge when jointly exploring transition relations together with response ranges of the transitions, we propose two heuristics for generating suitable response ranges prior to performing a DSE of proper enforcement FSMs. Our evaluation shows that the two proposed heuristics can generate efficient enforcement FSMs within a substantially smaller number of iterations (respectively time) compared to the case of using DSE to explore the joint space of transition relations and response ranges.

Non-volatile Memory (NVM) technologies present a promising alternative to traditional volatile memories such as SRAM and DRAM. Due to the limited availability of real NVM devices, simulators play a crucial role in architectural exploration and hardware-software co-design. This tutorial presents a simulation toolchain through four detailed case studies, showcasing its applicability to various domains of system design, including hybrid main-memory and cache, compute-in-memory, and wear-leveling design. These case studies provide the reader with practical insights on customizing the toolchain for their specific research needs. The source code is open-sourced.

Protecting the confidentiality of data at rest is a crucial concern for both individuals and organizations. While the XTS-AES encryption algorithm is commonly used to provide such protection, it was shown that Side-Channel Analysis (SCA) poses a threat to the confidentiality of the protected data. However, the attacks on software-based XTS-AES proposed in previous work focused on implementations for simple microcontrollers under idealized assumptions, but are not applicable on processor systems where branch predictors, caches, and operating systems introduce systemic noise to the side-channel signal. This paper discusses the challenges faced in SCA when the side-channel information is affected by such systemic noise and presents an end-to-end EM side-channel attack workflow to recover the XTS-AES key despite such noise and enable the decryption of protected data. After data acquisition, the resulting trace data, which may still be incomplete or error-prone due to systemic noise, is fed into our proposed attack flow targeting the individual cryptographic operations of XTS-AES: Our methodology applies timing analysis and profiling-based techniques in combination with an ASCAbased error correction to break the masking operations, and uses CPA to attack the AES encryption operations. Our side-channel attack approach is evaluated considering different implementations of the individual cryptographic operations using real EM side-channel traces captured from a BeagleBone Black SoC, with the application practicality of our attack being discussed based on the results.

Semi-structured data formats, such as JSON, are widely adopted in big data applications to achieve flexibility, fast integration and portability. As these formats are commonly highly sparse, compression is often applied before data is stored or transmitted over networks. However, since semi-structured records often need to be accessed individually, they need to be compressed separately, resulting in low compression factors when applying traditional Lempel-Ziv compression schemes. As a remedy, Fast Static Symbol Table (FSST) was proposed, a lightweight dictionary-based compression scheme specifically designed for short strings. In this paper, we present hardware acceleration techniques for the FSST compression scheme. Moreover, we evaluate the applicability of FSST to semi-structured data, such as JSON, and compare it to other compression schemes. Finally, in the evaluation of the presented accelerator circuits, we report speedups of 1.4 to 2.6 times and a reduction in energy consumption of 6.0 to 10.5 times compared to the open source FSST software implementation.

Abstract The available parallelism and heterogeneity of emerging computer systems must be exploited for being able to process the huge amounts of data produced every day. As a consequence, we observe an increasing research interest in accelerating database query processing on multi-cores and attached co-processors like Graphics Processing Units (GPUs) and Field-Programmable Gate Arrays (FPGAs). This chapter presents ReProVide, an approach combining near-data processing and FPGA-based acceleration. The System-on-Chip (SoC) architecture of ReProVide including a flexibly reconfigurable FPGA can load and execute hardware accelerators for various operators on relational and streaming data. Moreover, we present novel DBMS techniques for partitioning query-execution plans between a host and Reconfigurable data-Provider Units (RPUs) and for mapping operators onto RPUs by means of hardware reconfiguration.

Human-robot interaction (HRI) is characterized by a close collaboration between robots and humans and thus comes with a set of safety requirements on the robot execution that need to be guaranteed throughout this interaction. Several techniques have been proposed to specify the correct behavior of a robot that interacts with a human. The majority of them simulate the interaction in order to validate that the system is executing as specified. However, simulation is not enough to guarantee the safe behavior of a robot in presence of the uncertainty typically given by human behavior. In this paper, we suggest to apply runtime requirement enforcement (RRE) techniques using finite state machines (FSMs) to enforce a given set of safety requirements related to the interaction between a human and a robot, such as collision avoid-ance. We then suggest to apply formal verification techniques, i.e., probabilistic model checking to verify the probability of different safety requirements on two HRI scenarios. In addition, an analysis of the verification times is presented.

Computer systems are prone to crashes and power outages, particularly in intermittent computing scenarios where embedded systems rely on unreliable energy-harvesting sources. Hybrid caches, which integrate volatile and non-volatile memory (NVM) sections, offer opportunities for efficient operating system (OS) services to ensure data persistence over power interruptions. However, the lack of OS awareness of hybrid cache structures can result in inefficient backups, data loss and inconsistencies, as well as underutilization of the potential of hybrid caches. This paper introduces the Cache Hybridization-aware Operating System (CHaOS), that is based on a co-design of the OS and the underlying hardware to systematically persist volatile states and data in case of power outages. Our evaluation demonstrates that CHaOS not only proves robust against power outages, but also can significantly reduce the backup latency. In our test of using CHaOS to execute an image processing application on a hybrid-cache system, already with 75

Many battery-powered IoT sensor nodes rely on harvesting energy which must be assumed an unreliable source. Previous works have shown that a sensor node can adapt its power consumption to keep its battery’s state of charge at a sufficient level to achieve perpetual operation by, e.g., dynamically adapting its duty cycle. In this paper, we show that it is also possible to reduce the energy consumed by the operation of a sensor node by controlling the quality of the processed and transmitted data. Moreover, whereas most state-of-the-art methods rely on forecasting energy harvesting, risking loss of service in case of wrong predictions, this paper presents an algorithm called Guaranteed Remaining Energy Scheduling (GRES) which dynamically controls the quality of processed and transmitted data of a sensor node at runtime based on the state of charge of the battery, and providing a guarantee of safe continuous operation at the expense of data quality despite fluctuations in expected harvested energy. In experiments, GRES is evaluated and compared to an approach computing ILP-generated quality schedules for one full day ahead based on the assumption of a perfect harvested energy prediction. It is shown that the latter approach is not only computationally and energy-wise expensive, but also can lead to power shutdowns in case of wrongly predicted harvesting profiles.

Sound techniques for mapping soft real-time applications to resources are indispensable for meeting the application deadlines and minimizing objectives such as energy consumption, particularly on heterogeneous MPSoC architectures. For applications with input-dependent workload variations, static mappings are not able to sufficiently cope with the run-time variation, which can lead to deadline misses or unnecessary energy consumption. As a remedy, hybrid application mapping (HAM) techniques combine a design-time optimization with run-time management that adapts the mappings dynamically to the changes of the arriving input. This paper focuses on scenario-based HAM techniques. Here, the application input space is systematically clustered such that data inside the same scenario exhibit similar characteristics concerning workload when being processed under the same operating points. This static clustering of the input space into data scenarios has proven to be a good abstraction layer for simplifying the design and employment of high-quality run-time managers. However, existing state-of-the-art scenario-based HAM approaches neglect or underutilize the synergistic interplay between mapping selection and the usage of dynamic voltage/frequency scaling (DVFS) when adapting to workload variation. By combining mapping and DVFS selection, variations in the input can be either compensated by a complete re-mapping of the application, evoking a potential high reconfiguration overhead or by just changing the DVFS settings of the resources, offering a low-overhead adaptation alternative and thus significantly reducing the necessary overhead compared to DVFS-agnostic HAM. Furthermore, DVFS enables a fine-grained adaptation of a mapped application to the input data variation, e.g., by slowing down tasks with no impact on the end-to-end latency for the current input using low-frequency DVFS settings. It is shown that this combined approach can save even more energy than a pure mapping adaptation scheme, especially in the presence of data scenarios. In particular, scenario-based design operates as a catalyst for eliciting the synergies between a combined DVFS and mapping optimization and the peculiarities inside a data scenario, i.e., exploiting the commonalities inside a data scenario by perfectly tailored DVFS settings and task mapping. In this scope, this paper proposes two supplementary scenario-based DVFS-aware HAM approaches that consistently outperform existing state-of-the-art mapping approaches in terms of the number of deadline misses and energy consumption as we demonstrate in an empirical study on the basis of four different applications and three different architectures. It is also shown that these benefits still apply to target architectures with increasing mapping migration overheads, thwarting frequent mapping reconfigurations.

Embedded system applications normally come with a set of non-functional requirements defined over properties (e.g., latency), expressed as a corridor of correct values via a lower and an upper bound per requirement. These requirements should be guaranteed during each execution of an application program on a given MPSoC platform. This can be achieved using a reactive control loop, where an enforcer controls a set of properties to be enforced, e.g., by adapting the number of cores allocated to a program or by scaling the voltage/frequency mode of active processors. An enforcement strategy may react on a requirement response differently, depending on (a) satisfying a requirement, or violating (b) a lower bound or (c) an upper bound. A better strategy might be to differentiate the reaction taken according to the amount of violation of a lower or upper bound, thus to react in a finer granular way. In this paper, we propose a design space exploration (DSE) method called Co-explore that automatically partitions the requirement corridors into so-called response ranges (i.e., sub-corridors) such that formulated verification goals of simultaneously generated enforcer FSMs, e.g., the number of consecutive violations of a requirement, are optimized. The evaluation shows that the explored enforcement FSMs can achieve higher probabilities of meeting a given set of requirements compared to reacting solely based on the ternary information (a), (b), or (c).

The field of Non-Volatile Memory (NVM) is one of the most actively researched topics regarding disruptive memory technologies. A promising application of NVM lies in the hybridization of caches, combining both NVM and conventional SRAM to realize trade-offs, as NVM is expected to cause significant write overheads while offering a high density. Hybrid caches have gained importance in the field of intermittent computing on batteryless embedded devices, with non-volatile cache lines generally withstanding power outages. Replacement policies are employed to determine replacement candidates and whether to place data in volatile or non-volatile cache sections. Almost all known replacement policies require some type of metadata. Storing this metadata in NVM may generate additional write overheads as it is frequently accessed, while volatile metadata is lost after power outages. Losing this metadata may lead to unsuitable replacement decisions after regaining power, however it also cancels out any previously accumulated mispredictions. This paper examines the effect of different technological implementations of cache replacement policies on intermittently powered embedded systems employing hybrid caches. Our experiments show that the choice of technology for the replacement policy is an important design decision. Depending on the selected approach to store the metadata of the policies, we observe up to 28% in possible energy savings.

Big Data applications frequently process data streams encoded in semi-structured data formats such as JSON, Protobuf, or Avro. Parsing these data formats into a representation to then be processed by a CPU frequently takes up a major share of the processing time. As a remedy, JSON and Avro FPGA accelerators have been introduced that can parse the data directly in the data path, offloading this workload from the CPU without requiring any additional data movement. However, these accelerators are schema-specific circuits that require time-consuming resynthesis processes for schema adaptations. This is particularly critical in Big Data applications, where multiple schemas may be in use simultaneously. As a remedy, we present an application-specific instruction set processor (ASIP) architecture for parsing Avro data on FPGAs. An instruction program controls the ASIP to parse a specific schema. Any schema change therefore only requires the loading of a new instruction sequence into an instruction memory. It is also shown that this approach is more resource-efficient than related work, as functional units only need to be instantiated once for each Avro data type. Our experimental evaluation shows that we can achieve a throughput of 707-818 MB/s per kLUT which is about 7 to 14 times higher than the throughput per LUT achieved in related work.

Big Data applications frequently involve the processing of data streams encoded in semi-structured data formats such as JSON. A major challenge here is that the parsing of such data formats is usually highly complex. Accelerating JSON parsing on FPGAs has therefore become a focus of recent research. However, as JSON data is highly sparse, compression is frequently applied before writing records to storage or transmitting them over the network. Consequently, the data must be decompressed before parsing it into a suitable format for further processing.While existing work has addressed decompression and parsing of semi-structured data separately, we propose a co-design for JSON decompression/parsing. This co-design includes a compression scheme tailored specifically for JSON, along with an FPGA parser architecture capable of operating directly on compressed input data. Additionally, our design adopts a lazy decompression approach to only decompress projected attributes, thereby significantly reducing the workload on the decompressor. Our experimental evaluation shows that this co-design exploiting several synergies results in higher resource efficiency compared to existing approaches for JSON parsing on FPGAs, while also enabling the decompression of data. For high compression factors, we observe a 1.8 x increase in parsed JSON tuples per second and LUT compared to the most efficient related approach. Moreover, our presented compression scheme offers higher compression factors for JSON data than related work while providing similar performance.

Physical Side-Channel Analysis (SCA) is often restricted to less complex devices, such as microcontrollers, as more feature-rich targets, like microprocessor systems, contain possibly multiple sources of systemic noise that influence side-channels and their waveforms non-deterministically in the view of an observer. Thus, locating these waveforms using established waveform matching techniques and subsequent data association becomes impossible. This impedes the application of SCA techniques relying on the relationship of operation waveforms and their processed data. In order to address this issue, this paper presents the CRESTS algorithm, that is capable of locating instances of target operations in larger side-channel traces affected by systemic noise. This enables to extract the waveforms of the relevant operations from the trace and, by maintaining their overall sequence of occurrence, associate them with their corresponding data to then apply established SCA techniques. The effectiveness of our approach is evaluated by applying CRESTS on the widespread XTS-AES algorithm running on a Beaglebone Black System-on-Chip (SoC) target platform.

Digitizing side-channel signals at high sampling rates produces huge amounts of data, while side-channel analysis techniques only need those specific trace segments containing Cryptographic Operations (COs). For detecting these segments, waveform-matching techniques have been established comparing the signal with a template of the CO’s characteristic pattern. Real-time waveform matching requires highly parallel implementations as achieved by hardware design but also reconfigurability as provided by Field-Programmable Gate Arrays (FPGAs) to adapt the matching hardware to a specific CO pattern. However, currently proposed designs process the samples from analog-to-digital converters sequentially and can only process low sampling rates due to the limited clock speed of FPGAs. In this article, we present a parallel waveform-matching architecture capable of performing high-speed waveform matching on a high-end FPGA-based digitizer. We also present a workflow for calibrating the waveform-matching system to the specific pattern of the CO in the presence of hardware restrictions provided by the FPGA hardware. Our implementation enables waveform matching at 10 GS/s, offering a speedup of 50× compared to the fastest state-of-the-art implementation known to us. We demonstrate how to apply the technique for attacking the widespread XTS-AES algorithm using waveform matching to recover the encrypted tweak even in the presence of so-called systemic noise.

This paper explores the challenges and opportunities of integrating non-volatile memories (NVMs) into embedded systems for machine learning. NVMs offer advantages such as increased memory density, lower power consumption, non-volatility, and compute-in-memory capabilities. The paper focuses on integrating NVMs into embedded systems, particularly in intermittent computing, where systems operate during periods of available energy. NVM technologies bring persistence closer to the CPU core, enabling efficient designs for energy-constrained scenarios. Next, computation in resistive NVMs is explored, highlighting its potential for accelerating machine learning algorithms. However, challenges related to reliability and device non-idealities need to be addressed. The paper also discusses memory-centric machine learning, leveraging NVMs to overcome the memory wall challenge. By optimizing memory layouts and utilizing probabilistic decision tree execution and neural network sparsity, NVM-based systems can improve cache behavior and reduce unnecessary computations. In conclusion, the paper emphasizes the need for further research and optimization for the widespread adoption of NVMs in embedded systems presenting relevant challenges, especially for machine learning applications.

Soft real-time streaming applications often process input data that evoke varying workloads for their tasks. This may lead to high energy consumption or deadline misses in case their mapping onto a heterogeneous MPSoC target architecture is not adapted, e.g., when tasks with high execution times for the current input are assigned to resources of low computational power. To handle the vast variety of different input data, we propose to cluster data with similar execution characteristics into so-called data scenarios for which we determine specialized mappings by performing a scenario-aware design space exploration (DSE). A runtime manager (RTM) uses these mappings to adapt the execution of the running applications to their upcoming input by first identifying their best-suited scenarios. Subsequently, the RTM selects mappings considering their identified scenarios, which minimize the total number of deadline misses and the consumed energy. We embed the RTM into hybrid application mapping (HAM); ergo, performing time-consuming optimizations offline. In this article, we propose a novel data-scenario-aware HAM methodology that can cope with multiple applications and comprises two novel scenario-based mapping selection algorithms: Inter-Application Resource Mediation Mapping introduces barely any runtime overhead. Adaptive multi-app mapping selection is highly adaptive to changes in the application workload but imposes a small runtime overhead. Our HAM approach is fully automated and uses machine-learning techniques to learn the selection of suitable mappings from training data sequences at design time. Experiments on three differently complex target architectures show that our proposed approach consistently outperforms existing state-of-the-art solutions regarding the number of deadline misses and consumed energy.