Flexibility and customization make Field-Programmable Gate Arrays (FPGAs) attractive for arbitrary-precision arithmetic-heavy workloads such as sparse and mixed-precision DNN inference. However, in modern logic blocks, the hardware adder chain is typically driven only by look-up table (LUT) outputs, preventing adders and LUTs from being used independently and concurrently within a logic element, and reducing the hardware resource utilization efficiency. We propose Double-Duty , a logic block architecture that decouples LUTs and adder chains by augmenting four extra inputs of the logic element to bypass LUTs and directly drive the adders. We model the added circuits at the transistor level and implement full CAD support in open-source tools, including improved arithmetic synthesis to provide a realistic baseline. On a Stratix-10-like architecture, Double-Duty reduces area by 21.6% on Kratos adder-intensive circuits and by 9.3% and 8.2% on the Koios and VTR suites, respectively, improving average area-delay product by 9.7% across all benchmarks with minimal impact on critical path delay. Additionally, we combined Double-Duty with prior arithmetic-oriented optimized architectures, and the fused designs achieve up to 20% area-delay product reduction in geometric mean across multiple benchmarks compared to the baseline.
We present a flexible and scalable hardware/software framework for training CNNs on Ethernet-connected FPGA clusters using tightly pipelined layer parallelism. Starting from a high-level CNN and cluster description, the system automatically maps layers onto (potentially heterogeneous) devices, generates FPGA-specific bitstreams, and orchestrates fully streaming forward and backward passes while keeping most parameters and gradients in on-chip memory. We demonstrate support for general DAG-style CNNs, including MobileNetV2, MnasNet, and ResNet18, and replace batch normalization with online normalization to enable normalization in this streaming setting while achieving ImageNet validation accuracies comparable to PyTorch baselines with batch normalization for all three networks. A CP-SAT-based planner, driven by implementation-level resource estimates from SpinalHDL, performs resource-aware placement under constraints on DSPs, on-chip memory, DRAM bandwidth, and network bandwidth, and exposes FPGA-specific optimizations such as multipumped Matrix Multiplication engines, fabric-aware memory tiling, and activation recomputation. We evaluate throughput, resource utilization, and energy efficiency on an eight-board Altera Agilex 7 cluster and show that, for both MobileNetV2 and MnasNet, the framework achieves more than \(2\times\) lower energy per frame than Nvidia V100, A100, and H100 GPU baselines, highlighting the potential of FPGA-based, layer-parallel training for separable-convolution-dominated CNNs.
This work addresses the accurate (correctly rounded) evaluation of arbitrary functions. The simplest solution is to use a Look-Up Table (LUT), with a storage requirement (hence area) that grows linearly with the output word size, but exponentially with the input word size. This limits its applicability to small input word sizes. For monotonic functions, a binary search in the output domain enables implementations whose area scales linearly with the input word size and exponentially with the output word size. This article introduces several novel architectures exploiting this idea, investigates their efficient mapping to FPGA micro-architecture using features such as \(k\) -input LUT and fast carry logic, compares them to the LUT approach in area and delay, and demonstrates an application to a Gaussian pseudo-random number generator.
Although Fully Homomorphic Encryption (FHE) enables computation over encrypted data, its substantial computational and storage overhead remains a major obstacle to practical deployment. Among available hardware platforms, FPGAs offer a favorable balance of performance, flexibility, and energy efficiency, making them a promising option for FHE acceleration. This paper presents a systematic review of FPGA-based FHE accelerators published between 2011 and 2025, with a focus on architectural design and performance characterization. To enable consistent analysis across heterogeneous implementations, we develop a unified framework that models FHE execution in terms of computation and data movement and supports a roofline-based interpretation of performance. Applying this framework to representative designs shows that accelerator performance is jointly shaped by arithmetic parallelism, memory bandwidth, data reuse, and communication overhead, and that the dominant bottleneck is therefore architecture-dependent. Designs with limited data reuse or inefficient key delivery may remain bandwidth-bound, whereas kernel-level implementations and carefully batched streaming architectures can become compute-bound. Based on these observations, we identify key challenges in memory hierarchy design, bandwidth utilization, communication efficiency, and scalability, and discuss future directions including algorithm–hardware co-design, communication-aware architectures, and application-specific acceleration. Overall, this review provides a unified perspective on the performance bottlenecks and design trade-offs of FPGA-based FHE accelerators and offers practical guidance for future architecture development.
Designing computing systems for safety-critical platforms operating in harsh environments now demands balancing high computing performance with reliability and low-power execution. In New Space missions, for instance, Commercial Off-The-Shelf (COTS) devices are used as an alternative to Radiation Tolerant (RT) FPGAs and Radiation Hardened By Design (RHBD) ASICs, sacrificing reliability over pure computing power. Nevertheless, a bare minimum fault tolerance level needs to be ensured in order to successfully run the missions. Depending on the target fabric, multiple mitigation techniques can be implemented at the technology node, microarchitecture or system level. These mechanisms are typically complemented with intensive fault-injection and beam testing campaigns. Open Instruction Set Architectures (ISAs), like RISC-V, free from proprietary licensing constraints, allow controlled architectural variation across both COTS FPGA and ASIC fabrics, enabling easier fault injection/beam studies and Power-Performance-Area (PPA) analysis for competitive design development. This paper presents an open-source architectural template for accelerator deployment in safety-critical systems. The template, built around a triple-core RISC-V platform, integrates system-level reliability techniques that enable runtime-adaptive switching among Single, Triple-Core LockStep (TCLS), Dual-Core LockStep (DCLS), and DCLS with classical staggering modes. The template has also support for application-specific, hardware-based functional extensions, either via memory-mapped interfaces or through custom ISA extensions (attached to each of the triplicated cores using the standard CORE-V eXtension Interface). The capabilities of the proposed accelerator template have been tested both with a software-only implementation of the AES-128 data encryption algorithm and with an in-house implementation of the CCSDS 121 data compression algorithm, widely used in space applications, showing that the system-level reliability techniques can be straightforwardly extended to the hardware-accelerated functions as well. The assessment of the proposed accelerator template includes experimental evaluation of the reliability through a lightweight fault injection campaign, and both FPGA and TSMC 65 nm LP implementations.
Artifact evaluation (AE) is gaining traction across the computer science community as a means of advancing reproducible research and strengthening readers’ confidence in published results. Applying reproducibility to computer systems and architecture research has proven particularly challenging, and the FPGA community faces its own distinct hurdles—namely, the use of non-standard hardware platforms and dependence on specific software tools and versions. In this editorial, we review the history of AE in the FPGA community, compare it to practices in related fields, and discuss challenges and future directions. To date, AE has meaningfully improved the availability and accessibility of artifacts and their documentation, while also increasing readers’ confidence in published findings. Looking ahead, AE is poised to continue growing across the reconfigurable hardware community. Notably, ACM Transactions on Reconfigurable Technology and Systems will now offer AE with the opportunity to earn artifact badges for all accepted papers.
Communication often represents a critical bottleneck in the execution of deep neural networks (DNNs) on artificial intelligence (AI) accelerators. To improve communication efficiency, we propose HT-NoC (High-Throughput Network-on-Chip), a dynamically reconfigurable NoC that adapts its throughput to optimize internal resource utilization, thereby enabling the simultaneous transmission of a larger number of packets. Extensive evaluations across diverse DNN layers demonstrate that HT-NoC consistently outperforms a baseline non-reconfigurable mesh NoC. Specifically, HT-NoC accelerates the propagation of input parameters by up to \(4\times\) in fully connected (FC) and pointwise (PW) layers, while reducing dynamic energy consumption by \(2.6\times\) . For convolutional (CONV) and depthwise (DW) layers, HT-NoC achieves speedups of up to \(2.3\times\) and energy savings of \(2.15\times\) . Finally, when integrated into an AI dataflow accelerator, HT-NoC delivers a \(3.2\times\) speedup over systolic array (SA)-based accelerators in executing feed-forward network (FFN) blocks of Transformers. Importantly, these performance and energy improvements are achieved with minimal area, latency, and energy overheads introduced by the reconfiguration mechanism.
Efficient data reduction techniques, including deduplication and compression, are essential in storage systems, affecting performance and longevity. Existing data deduplication approaches often focus on intra-SSD deduplication, missing opportunities for cross-node deduplication, or have scalability issues when aiming for low latency and high-throughput data reduction on large-scale, distributed SSD arrays. We propose StreamDedup, a distributed stream accelerator implementing a transparent layer of deduplication as a network-attached, middle-tier service between the compute and storage tiers. StreamDedup manages all aspects of data deduplication and compression and can be seamlessly integrated into existing systems. It is RDMA-enabled and highly scalable, enhancing data processing capacities for large-scale storage systems. Our prototype, deployed on FPGAs, demonstrates that StreamDedup achieves a throughput of 12.7 GB/s on a single node, matching the network bandwidth of disaggregated storage, with a latency of less than 50 µs. Across 10 nodes, StreamDedup shows an almost linear increase in throughput with less than 60 µs of latency.
FPGAs are widely used for efficient CNN inference acceleration but designing high-performance accelerators demands significant hardware expertise. Existing solutions face limitations: hardware designs are often model/chip-specific with suboptimal resource efficiency, and compiler support is typically framework-restricted. To overcome these, we propose a generalized and flexible high-performance FPGA accelerator architecture and a flexible end-to-end compilation toolflow based on ONNX IR. The architecture features an optimized uint8 systolic array for high compute density and a dedicated X-bus module handling diverse convolution parameters. On-chip buffers and allocation algorithms enhance memory efficiency. Configurable design variables enable architectural adaptation and fine-tuning. Deploying four accelerator variants on a VCU118 board and compiling 17 CNN models demonstrated a peak convolutional throughput of 5,792.19 GOPS (99.82% of theoretical peak, 5,825.42 GOPS) and overall throughput up to 3,311.48 GOPS. Compared to prior work, our solution offers superior usability, greater flexibility, and higher performance under comparable DSP usage. Furthermore, across most tested models, it provides significantly lower latency and higher energy efficiency versus CPUs and GPUs.
Echo state networks (ESNs) are reservoir computing (RC) variants that offer comparable accuracy to standard recurrent neural networks at less cost for training, lower computation effort, and higher speed for inference. These characteristics make echo state networks highly suitable for resource-constrained edge implementations. In this article, we present an FPGA-based streamlined dataflow architecture for ESN inference. The accelerator quantizes all layers of the ESN and follows a direct logic implementation style that fully unrolls all computations. We introduce two variants of the accelerator, one that maps neurons to DSP blocks in the FPGA and another one that maps neurons solely to LUTs. We further elaborate on a tool flow to set up, optimize, and train an ESN model for a given dataset and then automatically generate the accelerator designs to be loaded onto an FPGA. We evaluate our accelerators on a number of time-series prediction and classification tasks and compare the errors and accuracies, respectively, for a 32-bit floating-point software baseline and our accelerators at different levels of quantization. We then compare our accelerator with prior work on FPGA-based implementations for ESN and with embedded GPU and CPU platforms. Our experiments show that our accelerators are resource-intensive but excel in latency, throughput, and energy efficiency. For an ESN model with 200 reservoir neurons, we achieve a latency of \(9.5\;\;ns\) , a throughput of \(100\) Megasamples/second, and a power-delay-product of \(72\;\;nWs\) . This outperforms all previous FPGA work and, compared to embedded GPU and CPU platforms, represents improvements in the order of several magnitudes.
The dependability assessment of critical systems must consider the emulation of transient faults, as they pose an important dependability threat for modern VLSI designs. FPGA-based systems are dominated by bit-flips in configuration memory (CM), which are relatively easy to emulate using partial runtime reconfiguration (RTR) FPGA fault injection (FFI) approaches. However, when FPGA is used as an ASIC prototyping platform, transient fault models representative of ASIC designs must be considered, such as bit-flips in sequential logic cells (Flip-Flops and on-chip RAM blocks). Existing RTR-FFI approaches do not adequately cover these faults, as they require the orchestrated manipulation of multiple CM bits for each target logic cell, and the location of these CM bits is unknown (not documented) for modern FPGA generations. This work experimentally formalises the mapping of the necessary CM bits, proposes an enhanced RTR-FFI methodology to emulate bit-flips in registers and on-chip RAMs of current-generation AMD Ultrascale+ FPGAs, and provides an upgraded publicly available open source FFI tool (BAFFI, https://gitlab.com/selene-riscv-platform/DAVOS ) supporting the proposed methodology. The validity of the proposed FFI approach is demonstrated by comparison with gate-level simulation-based fault injection in a case study of two soft-core processors (MC8051 and NOEL-V).
Heterogeneous FPGA platforms combining RISC-V processors and deep-learning accelerators are increasingly adopted in avionics and space, where performance must be paired with fault tolerance. We present RePAIR, a reconfigurable platform integrating an open-source RISC-V core with a TPU-like systolic-array accelerator for runtime fault detection, correction, and recovery. RePAIR extends the accelerator ISA with runtime self-test, enabling detection of structural faults in the array during inference. The platform supports dual inference modes: a plain mode with no overhead and a testing mode that performs checksum validation at a fixed cost of three extra cycles per matrix multiplication, with limited accelerator area overhead. Upon fault detection, the accelerator notifies the RISC-V processor, which triggers dynamic partial reconfiguration of the faulty region while preserving execution state, allowing inference to resume from the last correct step. Compared with full-device reconfiguration, recovery time is reduced by up to 900× on AMD KCU105 and 1400× on AMD ZCU102, while inference overhead remains ≤30% in the worst case. The methodology is hardware-agnostic and portable across FPGA devices, as shown by multi-platform implementations. Fault-injection campaigns combined with space-environment modeling estimate mean time to failure under mission conditions, demonstrating scalable and reliable FPGA-based AI acceleration for safety-critical applications.
Custom computing machines implemented on FPGAs have emerged as a powerful solution for tackling computationally intensive tasks, leveraging their capacity for deep pipelining and parallel memory access. Differential Evolution (DE), a robust optimization algorithm, combined with adaptive numerical integration methods, is widely used to optimize parameter values in diverse scientific models. These tasks involve extensive floating-point computations, making FPGAs an ideal platform for efficiently accelerating their execution. In this work, we present a flexible and scalable FPGA architecture optimized for DE. This architecture is tailored to solve complex, resource-intensive optimization problems and is easily customizable for various models and integration methods. To demonstrate its efficacy, we evaluate two case studies: The Hodgkin–Huxley model for neuron action potentials and the Circadian clock model of Arabidopsis thaliana . Our architecture integrates adaptive numerical methods with DE and achieves significant performance and energy efficiency gains over CPU and GPU implementations while maintaining versatility across applications. Our architecture’s modular design enables seamless adaptation across different scientific contexts, enabling further optimization of resource utilization and expansion of application domains. The results underline the potential of FPGAs as a superior platform for large-scale scientific computation, offering unmatched energy efficiency and computational throughput for highly demanding tasks. The code developed to carry out this work is publicly available at https://github.com/mdccUVa/de-fpga .
The increasing use of Deep Neural Network (DNN)-based applications on edge devices has imposed new computing challenges, as such workloads demand high computational capabilities while ensuring low power consumption. To address these challenges, enhancing the General-Purpose (GP) computing units of edge devices by integrating hardware accelerators with application-specific functions provides the flexibility to support diverse workloads, thereby improving computing efficiency. This article proposes a modular RISC-V co-processor capable of hosting multiple stream-based accelerator IPs in a scalable platform. A low-latency interconnect interfaces the IPs with a local multi-bank scratchpad memory and supports direct IP-to-IP communication. A custom instruction set complemented by software macros is used by a RISC-V core for configuration, execution, and memory management in the co-processor through the open source eXtension Interface. Decoupling the co-processor platform from the core clock domain using asynchronous FIFOs shows that the co-processor supports integration of up to 8 custom IPs and 16 memory banks at a frequency of 294–333 MHz, when prototyped on an AMD/Xilinx RFSoC 4 × 2 evaluation board, while consuming 3% or less of the LUTs available on the board. A ShuffleNet-V2 case study shows that the co-processor achieves comparable latency and up to 51% lower resource utilization compared to standalone HLS IPs.
The Bloom filter is one of the most widely used data structures in big data analytics to efficiently filter out vast amounts of noisy data. Bloom filters are used to accelerate many applications, including databases, networking, security, and bioinformatics. Unfortunately, prior Bloom filter designs only focus on single-input-stream acceleration and cannot match the increasing data rates offered by modern networks. The underlying problem is reading from the bit-vector, which requires fast random access. Since accesses are random, sharing the bit-vector is difficult due to dynamic access conflicts. However, naïvely duplicating the single-stream accelerator sacrifices scalability, due to the resource overhead of storing the entire bit-vector multiple times. We present BitBlender, the first scalable, high-throughput multi-input-stream Bloom filter acceleration framework in HLS. BitBlender’s architecture stores a large bit-vector in on-chip memories for ultra-low latency. Moreover, it efficiently shares access among all input streams to allow high throughput even for large Bloom filters with low false-positive rates. To enable this efficient shared access, we design and implement the novel Arbiter and Unshuffle modules to dynamically schedule conflicting accesses to execute sequentially and non-conflicting accesses to execute in parallel. To support different user configurations of the Bloom filter, we also develop an automation flow, together with an accurate performance estimator, to automatically generate the best BitBlender design to meet a user-provided Bloom filter specification. Experimental results show that, on the AMD/Xilinx Alveo U280 FPGA, BitBlender achieves a throughput up to 3,213 MQueries/s (i.e., 12.8 GB/s) for a 130Mib bit-vector with 0.005% false-positive rate. Compared to the highly optimized Rust crate fastbloom running on 24 CPU threads, it achieves an average speedup of 8.89×, up to a maximum of 10.47×. Compared to the naïvely-duplicated multi-stream FPGA design, it achieves an average speedup of 5.30×, up to a maximum of 7.42×. BitBlender is available at https://github.com/SFU-HiAccel/BitBlender .
The scientific community increasingly relies on Machine Learning (ML) for near-sensor processing, leveraging its strengths in tasks such as pattern recognition, anomaly detection, and real-time decision-making. These deployments demand accelerators that combine extremely high performance with programmability, ease of integration, and straightforward verification. We present cgra4ml , an open source, modular framework that generates parameterizable CGRA accelerators in synthesizable SystemVerilog RTL, tailored to common ML compute patterns found in scientific applications. The framework supports seamless system integration through AXI-compliant interfaces and open source DMA components, and it includes automatic firmware generation for programming the accelerator. A comprehensive verification suite and a runtime firmware stack further support deployment across diverse SoC platforms. cgra4ml provides a modular, full-stack infrastructure, including a Python API, SystemVerilog hardware, TCL toolflows, and a C runtime, which facilitates easy integration and experimentation, allowing scientists to focus on innovation rather than dealing with the intricacies of hardware design and optimization. We demonstrate the effectiveness of cgra4ml to implement common scientific edge neural networks using ASIC and FPGA design flows.
Content Addressable Memories (CAMs) offer high-speed, deterministic lookups but face significant scalability challenges with large input keys ( \( > \) 100 bits), leading to excessive power, silicon area, and memory costs. This article introduces Probabilistic CAM (P-CAM), a novel architecture designed to overcome these limitations by trading strict determinism for memory efficiency and scalability. P-CAM compresses high-dimensional inputs into fixed-size fingerprints using hashing, making memory requirements independent of key length. P-CAM preserves the constant-time lookup advantage of CAMs, while supporting applications with large keys, such as networking, bioinformatics, and machine learning, where conventional CAMs are impractical. FPGA implementation on Xilinx UltraScale+ devices shows that P-CAM maintains constant query latency and delivers 15 \(\times\) improvement in resource efficiency when handling 384-bit keys, compared to state-of-the-art deterministic CAMs designed for narrower inputs. Although P-CAM’s probabilistic nature introduces a small, controllable false-positive rate, it can be configured for fully deterministic operation under specific constraints. To the best of our knowledge, P-CAM is the first CAM architecture to employ a fingerprint-based probabilistic data structure as the primary storage mechanism for associative lookup, distinguishing it from prior probabilistic approaches that are limited to set membership checks, offering a robust and scalable alternative for modern data-intensive systems.
Monolithic integration of large FPGA dies increasingly encounters physical and economic constraints. Fully integrated 3D FPGAs remain commercially unavailable. Hence, interposer-based multi-die solutions (often referred to as 2.5D FPGAs) have emerged as a practical and scalable alternative. These architectures offer higher integration density, improved yield, and enhanced performance scalability by circumventing limitations imposed by reticle size and the complexities of manufacturing large monolithic dies. Interposers facilitate high-bandwidth, low-latency communication between multiple FPGA dies within a single package, making them a promising bridge technology. However, distributing an FPGA design across multiple dies makes placement and routing challenging. While general FPGA placement has been the subject of various surveys, no existing work focuses specifically on the unique challenges, design considerations, and state-of-the-art techniques associated with placement in 2.5D multi-die FPGAs. This survey aims to fill that gap and provide insights into this rapidly evolving field.
