Traditional FPGAs suffer from long reconfiguration latencies, ranging from milliseconds to seconds, which significantly limits their usage in applications that require rapid multi-context switching and dynamic partial reconfiguration. To overcome this barrier, we propose vertical FPGA (vFPGA), a novel 3D FPGA and packaging co-design methodology that leverages advanced packaging to achieve sub-mu s full-chip reconfiguration, while maximizing the on-chip storage capacity for multiple configuration contexts. In vFPGA, we partition a 2D FPGA die into two dies: a bottom die with the conventional programmable fabric, and a top die with memory banks and control logic to store multiple configuration contexts. These two dies are interconnected face-to-face through high density, vertical connections, such as micro bumps, Cu pillars, or hybrid bonding, which enable high-throughput, parallel programming paths that rapidly reconfigure the bottom die. Using the OpenFPGA framework with GlobalFoundries (GF) 22nm FDSOI process technology, we design both dies and conduct a comprehensive design space exploration (DSE) in light of packaging technology scaling. Our DSE focuses on the co-design of the pitch and dimensions of vertical interconnects, logic fabric partitioning, scan-chain partitioning, and memory bank selection and layout, with the objective of minimizing reconfiguration latency. In the physical implementation of 3D die-to-die integration, we also address critical signal integrity issues including clock synchronization and electrostatic discharge (ESD), along with power delivery challenges. Our simulation results demonstrate that, with 22nm dies and 45 mu m Cu pillar pitch, our new 3D FPGA achieves a sub-mu s reconfiguration latency, independent of the FPGA die size, yielding a 1,000x faster reconfiguration over traditional 2D FPGAs. Moreover, with hybrid bonding as vertical interconnects, we achieve sub-10 ns reconfiguration latency.
This paper presents Gatling-V1, an FPGA-optimized implementation of the RISC-V Vector extension that concurrently executes up to four vector instructions. The main innovation is using a multi-banked ASIC approach to build a vector register file from simple dual-port (1R1W) BRAMs rather than using traditional FPGA-based multi-port techniques. This saves both logic and BRAM, improves clock speed, and supports multiple overlapping in-flight instructions as well as vector chaining. However, it is limited to launching one vector instruction every two cycles. Using this technique, we build a RISC-V vector core that runs at 500MHz on AMD UltraScale+ HBM (16nm) with a 4R4W/8R8W register file and 2/4 fully parallel ALUs that use chaining (convoying) to reach peak utilization on sequentially dependent (independent) instructions with vectors longer than 36/72 (4/8) elements of 64b words, respectively. On microbenchmarks, the 4-ALU implementation is over 6 times faster than Saturn-V, an FPGA-optimized RISC-V vector engine, while consuming only twice as many LUTs but similar BRAMs and DSPs.
Large-scale multi-FPGA systems are widely used in modern emulation systems. As a critical part of the multi-FPGA system design flow, TDM signal grouping and package pin assignment directly impact the final placement and routing in the FPGA physical implementation. Poor pin assignments cause severe congestion and timing degradation at the logic-element level, while existing approaches lack accurate congestion modeling during system-level partitioning. This paper presents Chimew, a novel pin assignment methodology that leverages placement prototyping to predict logic-element-level congestion before physical implementation precisely. The proposed method co-optimizes signal grouping and pin placement through iterative refinement guided by congestion-aware cost functions derived from fast global placement. Experimental results demonstrate a 28% congestion reduction and up to 2.87ns less worst negative slack (WNS) compared to industrial tools while achieving a 100% success rate across diverse multi-FPGA benchmarks.
