Recent advances in neural network design have emphasized attention-based Transformer models, which deliver state-of-the-art accuracy across applications in natural language processing and computer vision. However, the computational demands of Transformers pose significant challenges for deployment in latency-sensitive scenarios and resource-constrained devices, resulting from Transformers' quadratic scaling to sequence length in attention mechanism and extensive data movement. Many works have tried to alleviate these limitations while failing to give comprehensive solutions that consider the heterogeneous characteristics within Transformers. In this paper, we propose RECONFORMER, a system-on-chip that accelerates Transformers through multi-level reconfigurability. At component level, RECONFORMER introduces reconfigurable processing elements by incorporating range-based approximations for non-linear functions, resulting in 21% reduced logic usage per accelerator. At the system level, RECONFORMER has a run-time coarse-grained reconfigurability, which provides adaptive parallelism strategies and dynamic cache-coherence mode to address diverse kernel requirements. As a result, RECONFORMER achieves up to 5.54x speedup in multi-head attention and 3.61x in end-to-end performance improvement over a static system. RECONFORMER attains remarkable performance compared to other platforms, resulting in 13.03x and 5.30x higher efficiency than edge and server CPUs, respectively. Even compared to an edge GPU, RECONFORMER achieves 1.79x improvement in efficiency, highlighting our system as a compelling alternative for edge deployment.
Developing FPGA applications, either using RTL or HLS, requires knowledge about the platform on which the application will be deployed. The availability of resources changes according to each FPGA model. To deal with this, the components of applications may be implemented using different primitives. For example, Floating-Point operations can be implemented using Flip-Flops and Look-up Tables, or with the addition of DSP units, the same happens for other components, such as FIFOs. During development, the implementation of the components is often chosen and used for the rest of the design. Using Integer Programming, this work explores how different floating-point implementations can be mixed to achieve performance optimization in a stencil application. Furthermore, it discusses how the same idea can be used for other components and applications.
Field-Programmable Gate Array (FPGA) routing is computationally expensive, taking hours or days with no guarantee of success. While prior work has used machine learning (ML) to guide placement and routing or predict routing outcomes, the process remains challenging to model precisely. This demo presents a new machine learning-based tool that addresses this problem.
The prefabricated resources in a field-programmable gate array (FPGA) can pose challenges resulting in unexpectedly long routing times. This sometimes leads to FPGA engineers prematurely terminating a viable routing run because they mistakenly believe the lengthy runtime indicates an unroutable design. In other cases, the FPGA engineer may wait long periods of time on a run that is doomed to never converge to a solution. As this leads to time wasted on runs which never reach design closure in either case, it is ideal to instead have an ML model decide whether or not to terminate routing. In this work, we introduce data-driven machine learning (ML) techniques for predicting both FPGA design routability and routing runtime continuously during routing.
The recent edge computing such as the Internet of Things needs to handle a large amount of data streams such as generated from sensory and video devices. To enhance the application performance, one of the major techniques is to reduce the data amount and accelerates the communication performance. We proposed a reconfigurable lossless data compression technique called Adaptive Stream-based Entropy (ASE) coding that handles such continuous data stream at high data rate. Our demonstration shows energy impact for a system that has a data sink in memory devices by reducing the number of the I/O accesses applying ASE coding. We implemented a system with an FPGA that handled video data stream with buffering compressed video frames to DDR3 DRAM and also displays the original video stream on a monitor. The system improves energy consumption of the memory devices without performance degradation.
