The Electrocardiogram (ECG) is a graphical representation of the electrical activity of the heart that is captured through a non-invasive process and is used to monitor the state of the heart. Because of its low power, ECG signal is often contaminated with different types of noises. Noisy ECG recording often leads to misinterpretation of heart disease. Hence, denoising of ECG signal is utmost important for accurate assessment of heart health. Addressing this issue, the paper presents a real-time composite digital filter model that attenuates noise from a corrupted ECG signal. The proposed model integrates three classical digital filters: an elliptic high pass infinite impulse response (IIR) filter, moving average (MA) type finite impulse response (FIR) low pass filter, and IIR elliptic band stop filter. All filters are realized using transposed structure and implemented on FPGA platform. The soft model is developed through graphical programing in MATLAB Simulink by using only basic Xilinx System Generator (XSG) blocks and is emulated in Zedboard Zynq-7000 FPGA board. For hardware emulation of the model, 2.61% of total available resource is utilized and 0.278 W on-chip power is consumed. The Worst Negative Slack (WNS) for our design is 2.789 ns, indicating that it meets all required time constraints and the hardware implementation of the soft design is successful on the FPGA board. The model is tested using 376 ECG recordings from the MIT-BIH Normal Sinus Rhythm, MIT-BIH Arrhythmia, and ECG-ID databases. Additionally, we have introduced various noise signals from the MIT-BIH Noise Stress Test database and synthetically generated in MATLAB to further corrupt the ECG signals. The average improvement in signal-to-noise ratio (SNRimp) achieved by our model is 7.61 dB for the ECG-ID database, 6.9 dB for the MIT-BIH Arrhythmia database, and 8.42 dB for the MIT-BIH Normal Sinus Rhythm database. The average root mean square error (RMSE) values are 0.0975, 0.2616, and 0.2168, and the average percentage root mean square difference (%PRD) values are 77.91, 64.11, and 68.21 are computed, respectively.
We investigated osmotic energy generation in a bioinspired nanochannel with grafted polyelectrolyte layer (PEL) by varying the porosity of the PEL. Using finite element based numerical solver, we solved the governing transport equations numerically. In the limiting scenario, we validated our numerical model using theoretical result. We thoroughly studied the cationic concentration field, axial electric field, cationic and anionic current, transference number, net current, diffused potential, maximum power density, and maximum energy conversion efficiency by altering the PEL porosity and the concentration of salt in the left-side reservoir. Together with the changes in reservoir concentration, we found that the PEL porosity significantly influences the axial electric field intensity and cationic concentration field. For the reservoir concentration below the critical limit, it was found that the power density increases with PEL porosity. The highest energy conversion efficiency, on the other hand, was shown to be decreasing as the polyelectrolyte’s porosity increased. The findings of this study contribute to a better understanding of the effects of polyelectrolyte porosity on osmotic energy generation and may aid in the design of high-power density renewable energy generation devices.
This article presents a novel hybrid coupled-inductor (CI) cascaded high step-up (HCICHSU) DC-DC converter tailored for renewable energy systems. The proposed converter achieves ultrahigh voltage gain, low voltage stress on semiconductor devices, and continuous input current by combining buck-boost and boost topologies within a hybrid cascaded structure. The topology targets large conversion at a moderate duty cycle while keeping device stresses low and maintaining a smooth input current. Continuous-conduction operation is analyzed, and expressions for voltage gain, device stresses, and component sizing are derived. A loss model and sensitivity discussion identify dominant loss mechanisms at high conversion ratios. For control, a small-signal model is developed, and the inherent right-half-plane zero (RHPZ) is handled using a Type-III compensator. Experimental verification uses a 160 W prototype stepping 24 to 200 V. The converter reaches 94.4% efficiency at full load and limits drain-to-source peak voltages to about 48 and 60 V for the two main switches, confirming effective leakage-energy recovery and stress reduction in practice. Measured waveforms show stable regulation and consistent currents.
This work focuses on designing a winner-take-all (WTA) algorithm using digital circuits, rather than the more commonly used analog circuits. In this context, neurons are represented as digital bits, similar to those in convolutional neural networks (CNNs) and weightless neural networks (WNNs). The proposed WTA circuit compares the most significant bits (MSBs) of all neurons (or discriminators) in parallel. The results of this initial comparison are then used to evaluate the second MSBs, where a parallel comparison is performed. This process continues iteratively for each subsequent bit until the least significant bits (LSBs) are analyzed. By removing less significant neurons early in the process, the number of signals that switch activity in subsequent comparisons is decreased, thereby reducing overall dynamic power. The WTA circuit consists of an array of OR-AND configurations that employ low-cost CMOS logic gates and operate without a clock or any form of synchronization. This design inherits the advantages of scalability and configurability: adding a new neuron requires only inserting a new row of cells, while increasing the size of the neurons can be accomplished by adding new columns of cells. The design characteristics rely on two factors: the number of neurons (K) and the size of each neuron (N bits). Neuron size plays a crucial role in determining the critical path delay.
This paper introduces a novel image-denoising technique that integrates a hybrid deep learning (DL) model with a self-improved orca predation (SOP) strategy. This hybrid model improves denoising performance by integrating a Convolutional Neural Network (CNN) with Bidirectional Long Short-Term Memory (Bi-LSTM). The hybrid model’s hyperparameters are enhanced using the SOP technique, resulting in superior denoising outcomes. The proposed approach is experimentally tested with the INbreast and CBIS-DDSM datasets. The results demonstrate that the suggested method outperforms conventional approaches, making it a viable option for image-denoising applications. The suggested technique achieved a PSNR of 35.905 on the INbreast dataset and 37.08 on the CBIS-DDSM dataset. However, the DL model demands a significant amount of memory and computing capacity, limiting its implementation on edge devices and causing computing delays and energy loss. Field Programmable Gate Arrays (FPGAs) are ideal for practical applications due to their high computational capability and low power consumption. In this paper, we implement the proposed model on a ZCU104 FPGA board, evaluate its performance, and analyze resource utilization. The experimental outcome shows that the proposed network on the chosen FPGA achieves an impressive execution time of 4.25 s, low power consumption of 3.2 W, and a throughput of 47 images per second.
The performance of conventional phase-frequency detectors (PFDs) is critically limited by dead-zone and blind-zone artifacts, which stem from the timing constraints of D flip-flop (DFF) based architectures. These non-idealities degrade phase-detection resolution, induce cycle slip, and prolong the lock time of phase-locked loops (PLLs). This paper introduces a dual-edge low-duty-cycle PFD (DELD-PFD) that utilizes high-speed feed-through and output-prediction logic flip-flops to detect both rising and falling edges of the input clocks, thereby eliminating the dead and blind zones and enhancing phase resolution. The proposed architecture inherently generates low-duty-cycle output pulses, which reduces charge-pump current mismatch and improves loop dynamics. Fabricated in a standard 55 nm CMOS technology, the post-layout simulation results validate operation across 1 MHz-5.5 GHz. The DELD-PFD achieves a lock-time reduction of 63% relative to a conventional PLL, consumes 74 & micro;W at 5 GHz from a 1.2 V supply, and delivers a phase noise of -147 dBc/Hz at a 1 MHz offset. Comprehensive Monte Carlo and PVT (process, voltage, and temperature) simulations confirm robustness across variations, demonstrating the design's suitability for high-speed, low-noise, frequency-hopping PLL applications.
This paper introduces an efficient solar cell simulator. The simulator can simulate various combinations of materials. The simulator provides a lot of flexibility to the user to design the solar cell. This simulator supports group IV, II–VI and III–V material systems. The simulator gives flexibility to the user to simulate different sections of the cell individually before the final stage, which guides the user to design the efficient solar cell for his/her requirement. The simulator is quite simple, and the user has a lot of choices, such as material selection, changing dimensions, number of layers, nanostructures, and their parameters. This simulator will be helpful for both research and academic purposes.
As widely used in arithmetic circuits (such as a ripple carry adder [RCA]), approximate computing intentionally introduces errors in the design; however, approximate circuits can also experience errors due to external and physical phenomena (such as cosmic rays or a stuck-at). These errors can be analyzed by their functional nature. This article examines the impact of a single functional error (SFE) in both an approximate cell as well as the entire RCA. The study analyzes exact and approximate cell designs using a state transition diagram-based approach to understand the relationships between different types of functional error and the expected behavior in all possible scenarios. The article also proposes a probabilistic analysis for an exact RCA, which aligns well with simulation results for several metrics, such as the error rate (ER). Additionally, an error analysis is conducted on the RCA by considering the number of approximate cells and the location of the single erroneous cell. The results and modeling analysis of the exact RCA show that the ER and the mean error distance (MED) for Carry in (Cin) = 0 are higher than for Cin = 1; furthermore, the MED for an approximate RCA in the presence of an SFE is higher than for the exact RCA. These findings indicate that an approximate RCA affected by an SFE incurs a significantly degraded accuracy as related to the approximate cell type. Finally, the article provides a binary tree-based analysis to support the comprehensive simulation results for the RCA’s ER using different approximate cells.
This work introduces a novel method to improve hardware debugging efficiency and decrease computing time by employing a finite state machine (FSM)-based reconfigurable buffer insertion strategy for optimizing field-programmable gate array (FPGA) performance. The proposed strategy greatly enhances the debugging process by offering a systematic approach for error discovery, so ensuring that the FPGA functions with diminished complexity and increased dependability. Additionally, a reconfigurable decision tree generation (DTG)-finite impulse response (FIR) filter design is shown to optimize circuit area, resulting in a decrease in the quantity of stored memory look-up tables (LUTs). The substantial enhancement in power efficiency and area attained by using 4 LUTs in place of 6 LUTs. This work executes and verifies the register-transfer level (RTL) functionality by operating with 16 taps. This idea depends on the usage of an FSM controller for the utilization of a common buffer. This buffer eliminates the usage of 16 distinct buffers by sharing all 16 taps in order to identify errors. With this approach, the simplified design and overall efficiency are improved. This approach achieves improved debug capabilities with a single common buffer by eliminating usage of multiple buffers. The hardware complexity of the circuit is decreased substantially by using this proposed model. This model proves that the suggested FSM-based buffer insertion and reconfigurable FIR filter design improve computational efficiency and FPGA area optimization, positioning it as a viable alternative for forthcoming FPGA-based designs.
Taking advantage of cutting-edge technologies to efficiently control energy consumption while prioritizing public well-being is a wise choice for the sustainable development of cities and societies. From this perspective, the proposed approach in this study, which employs real-time electricity pricing, user age, and user preferences as input parameters for a fuzzy inference system (FIS), aims to balance energy consumption along with people’s lighting requirements. FISs based on linguistic patterns are ideal for establishing communication between individuals and artificial intelligence, especially in smart cities. FIS allows complicated parameters to be defined in a flexible framework that is easily understandable to humans. While this study specifically evaluated the performance of the proposed system for lighting demands, it may also be applied to other purposes and requirements. Results from the system simulations for a commercial setting validate the suggested system’s accuracy. According to the findings, developing appropriate control strategies derived from the established method enables meeting users’ lighting requirements for individuals of different ages. At the same time, this method regulates energy consumption and associated costs. The introduced method is advocated as an innovative solution for developing smarter and more sustainable cities and societies.
Typical resonant converter controllers are based on linearised averaged models, which have significant modelling errors when there are wide fluctuations in the input voltage, load and reference voltages. In this article, a piecewise affine (PWA) switching surface with active border tuning of affine sections, called the Partition Border Tuning (PBT) controller, is proposed for DC-DC series resonant converters (SRCs). Lyapunov stability analysis is used to ensure closed-loop stability. A new Chattering Mitigation (CM) technique is proposed to suppress unwanted oscillations between modes and output voltage overshoot under transient conditions, which are generally present in conventional switching surface controllers. This technique eliminates chattering, reduces output voltage overshoot and limits the maximum inductor current and capacitor voltage amplitude of the resonant tank under transient conditions. Simulation and experimental data are presented to demonstrate the effectiveness of the proposed approach.
Aiming at the modeling problem of bipolar distributed photovoltaic (DPV) cluster, this paper proposes a clustering equivalent modeling method based on clustering algorithm. First, by analyzing the detailed model of bipolar DPV, it is found that the indexes that can reflect its steady-state and dynamic characteristics mainly include energy storage element parameters such as inductance and capacitance and PI control parameters. Then, combined with the five commonly used clustering algorithms, the clusters composed of ten DPVs are clustered and grouped. Finally, the dynamic simplified model of DPV cluster is obtained by parameter aggregation and model equivalence of DPV in the same group. The above analysis is simulated and verified on the IEEE33 node system containing 10 DPVs, and the traditional single-machine equivalent model and double-machine equivalent model and clustering model are added for comparative analysis. The simulation results show that the clustering equivalent model can correctly reflect the dynamic response characteristics of DPV clusters under different working conditions. The error between each clustering model and the detailed model is not more than 10%. Among them, the fuzzy C-mean (FCM) clustering model has the best effect, the minimum error is 0.11%, and the maximum error of the single machine equivalent model is 9.3%.
Today, the latest impressive evolution and adaptation has been achieved by VLSI technology and advancement for smart industries is also going on this field. To reach these platforms, this credit goes to scaling down the aspect ratio. The measurements of the MOSFETs have not been reduced, but also the rebellion is moving all circuits from MOSFET to one new emerging device. This paper highlights the analysis of the new issue of reliability, i.e., noise voltage which affecting the SRAM cell retention voltage. For comparison with the effect of aspect ratio using Cadence Virtuoso tool, simulation results are taken on the Memristor based 8T SRAM cell and the conventional 8T SRAM cell with 45 nm technology. This article is protected by copyright. All rights reserved.
In modern industrial production, CNC (Computerised Numerical Control) machine tools are very common equipment. and related technologies are also developing vigorously. Its structure and related accessories become more and more complex. Under this condition, CNC machine tools are very prone to failure, so the fault diagnosis of CNC machine tools is particularly important. However, the actual operation of the machine tool is very complex. At present, mechanical diagnosis has the problem of single sensor information. On this basis, this paper proposes a method of mechanical fault diagnosis of CNC machine tool system based on data information fusion, and studies the optimization design of traditional mechanical fault diagnosis through the common calculation method in D‐S evidence theory(dempster‐shafer evidence theory). Through testing the mechanical fault diagnosis system of CNC machine tool system designed in this paper, the accuracy of fault detection is 95.50%, 96.32%, 90.12%, 94.43% respectively, and the accuracy index of fault location was 0.85; the satisfaction of factory maintenance personnel reached 88% after use. According to the above data, it can be judged that the mechanical fault diagnosis system of CNC machine tool system based on data information fusion has obvious advantages for the traditional diagnosis system, and has the value of in‐depth research. This article is protected by copyright. All rights reserved.
Integrity is an important index of document inspection in power sector, which is of great significance to document management and later search. However, the integrity of documents in the power sector is generally poor, which cannot meet the requirements of comprehensive inspection. Multi‐modal key method can analyze the integrity of enterprise archives from multiple angles, not only analyze the data integrity of archives, but also comprehensively judge other attributes of archives, which makes the analysis results more comprehensive. Aiming at the problem that the integrity of archives cannot be judged accurately in the filing process of electric power enterprises, a key verification algorithm based on multi‐modality is proposed. Firstly, the multi‐modal analysis of archives information data is carried out, and the enterprise archives archiving data set is constructed, and the legitimacy of the data set is verified; Using multi‐modal theory, the archives of electric power enterprises are divided into modal subsets, and each modal subset chooses the key verification algorithm; Finally, under the guidance of multimodal theory, modal subsets can accurately archive files. MATLAB simulation results show that the key check algorithm based on multi‐modality can improve the integrity of enterprise archives and shorten the archiving time under massive archives information, which is superior to previous archiving methods and meets the archiving needs of power enterprises. Therefore, the algorithm proposed in this paper is more reasonable, can simplify the document data, reduce the complexity of analysis, and is suitable for massive document analysis. This article is protected by copyright. All rights reserved.
Both circuit performance and long-term reliability are significantly impacted by the combined effects of temperature-induced drive current fluctuations and self-heating in FinFET devices. The performance of a three-stage rail-to-rail dynamic comparator based on a 7 nm FinFET is examined in this work, taking into account the effects of thermal changes caused by supply voltage and input voltage (Delta Vin) as well as bias temperature instability (BTI) stress. When compared to traditional bulk CMOS comparators, FinFET-based three-stage rail-to-rail dynamic comparators show essentially different delay-temperature characteristics, according to extensive HSPICE simulations. Even in the super-threshold supply voltage domain, the 7 nm FinFET-based design shows decreased delay but increased power consumption as temperature rises, in contrast to CMOS comparators, where delay usually increases with temperature. However, at high temperatures, leakage power dissipation increases dramatically, resulting in a loss of performance. With immediate applications in ultralow-power Internet of Things (IoT) nodes, sophisticated memory sense amplifiers, high-frequency communication systems, and portable biomedical equipment, these insights are especially helpful in directing the design of next-generation high-speed and energy-efficient mixed-signal circuits.
This paper presents the design of an integrated wideband active coupler, using a universal structure designed for 45 degrees and 180 degrees, to realize arbitrary phase shifts below 90 degrees and above 90 degrees, respectively, by adjusting a pair of capacitors in the coupler. Furthermore, continuous phase shifts within the ranges of 180 degrees-135 degrees and 40 degrees-90 degrees are achieved. The variable capacitor in the passive network (PN) is implemented using variable capacitance, implemented by a transistor and by adjusting dimensions and gate-source biasing. Each PN in the coupler is configured as a fifth-order low-pass filter, designed by transfer matrix analysis. A systematic design procedure based on this analysis is introduced, illustrating the combination of staggering technique, lumped-element compensation, and multisection impedance transformation to provide low output phase error and improved directivity. Measurements conducted on fabricated chips in GaAs technology for the 180 degrees (45 degrees) coupler within the frequency range of 10-20 GHz reveal an output phase of 180 degrees +/- 1.5 degrees (45 degrees +/- 1 degrees), return loss better than 15 dB (15 dB), directivity greater than 30 dB (35 dB), and a coupling gain at the center frequency equal to 6 dB (5.2 dB). Continuously tunable output phase couplers for the phase ranges of 40 degrees-90 degrees and 180 degrees-135 degrees are achieved, based on the proposed universal structure, for each 2 GHz bandwidth in 12-14 GHz band. Within this frequency range, impedance matching around -10 dB and phase error of +/- 1 degrees are obtained. Comparable performance is observed in each 1 GHz sub-band within the 14-20 GHz range. Additionally, simulation of the above couplers in 180 nm CMOS technology domonstrates similar performance.
Due to process deviations (Devs) in Micro LEDs, the luminous efficiency of each individual Micro LED can differ. Consequently, this leads to uneven luminance across the Micro LED matrix panel. In this study, a correction algorithm is proposed with the aim of improving luminance inhomogeneity on the panel. The brightness value of each pixel point on the LED panel is measured using a camera. Since the panel’s position may shift during detection, our approach incorporates self-detection and position correction to handle such misalignments. This eliminates the need for manually aligning the LED module to a fixed position on mechanical fixtures in our calibration system. The embedded system uses a camera to detect panel brightness and then generates correction coefficients for individual LED. Afterward, the coefficients are loaded into the FPGA control board and stored in memory as a Look-Up Table (LUT). Pixel correction on the Micro LED panel is achieved by selecting the corresponding coefficient from the LUT for each pixel position. The same procedures are iteratively performed ~3–4 times, using recursive processing to achieve superior uniformity across the Micro LED panel.
Approximate computing (AC)-based arithmetic circuits have not been reliable in sensitive applications like difference detection of bioimages. This article declares that the challenge is not established constantly. Accordingly, a new AC-based compressor with 16 transistors based on compound gates is proposed. The cell is implemented by complementary metal–oxide-semiconductor (CMOS) technology, and a novel approximate sum of absolute differences (SADs) unit is proposed using the compressor. Also, an error-correction module (ECM) is presented to improve the accuracy and error reduction of approximate SAD. The circuit performance and the accuracy of the output image after embedding the compressor in SAD are extracted, and the results show the superiority of the proposed circuits. The acceptable accuracy and performance of the SAD are proven versus standard and bioimages. In comparison with the exact type, the represented approximate 4:2 compressor reduces the power and power-delay-product (PDP) by 80% and 96%, respectively, while the utilization of the proposed compressor in SAD decreases the average power by 35% and reduces 43% of the average PDP. The quality and accuracy of the figure of merits (FoMs) support the main idea of this study for a new generation of AC-based circuits that are applicable in bioimage processing.
This paper presents a new method for direct sampling of the backscattered signal in ultrawideband (UWB) impulse radar for vital sign detection. One of the standard methods for direct sampling in UWB radars is the time-interleaving technique. In these converters, NOT gates (logical inverter gates) and tunable delay cells are typically used to create time delays and generate delayed replicas of the sampling clock. However, the challenge arises from the nonuniform delay associated with these gates and dependency on the process, voltage, and temperature (PVT), which affects the converter spurious-free dynamic range (SFDR). This paper employs a new structure using a ring counter to overcome this issue. As a result, a stable and PVT-independent sampling clock is obtained without significant overhead, compared to the conventional inverter-based delay cells approach. The proposed flip-flop-based ring counter architecture eliminates the need for analog delay tuning, offering a fully digital, PVT-resilient solution for uniform sampling in high-speed radar systems. The proposed structure has been utilized to design a 12-channel, six-bit time-interleaved swept-threshold analog to digital converter (ADC). The ADC has been in 65 nm complementary metal-oxide-semiconductor (CMOS) technology and simulated using the foundry design kit. Postlayout simulation results demonstrate a total power consumption of 28.54 mW with a 16.66 GS/s sampling rate.
