The AMD Versal ACAP provides a powerful heterogeneous architecture for accelerating kernels like general matrix multiplication (GEMM). Because the AI Engine (AIE) array mimics the spatial regularity of a systolic array (SA), mapping SA dataflows onto the fabric is highly intuitive. However, maximizing performance requires overcoming specific coordination challenges between data movement and compute cores. In this work, we demonstrate that the gap between theoretical peak and realized performance is the result of a fundamental "Systolic Tax" imposed by the AIE architecture. We provide a systematic study of 2D systolic mapping to quantify the architectural cost incurred when traditional wavefront data forwarding consumes execution cycles otherwise available for processing. This engine-level overhead leads to a simulated 8.2% compute cycle loss. To address this constraint, we implement a multicast-based SA (MCSA) design that leverages hardware multicasting for efficient operand delivery. This design is supported by a Mixed-Integer Non-Linear Programming model used for architectural optimization. Our design achieves a programmable logic frequency that analytically saturates the logic-engine communication bandwidth. While MCSA delivers a 1.28× throughput improvement over prior state-of-the-art systolic mappings, performance is ultimately limited by synchronization overhead, establishing a ceiling for systolic designs on these platforms and revealing the lack of parallel AIE-initiated data movement as a critical architectural bottleneck.
Foundation models such as SARATR-X have advanced Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR) by learning generalizable representations. Unlike standard Vision Transformers (ViTs), SARATR-X employs a hierarchical transformer with multi-stage feature extraction, deeper attention layers, and Relative Positional Encoding (RPE). While these enhancements improve SAR target recognition, they introduce significant challenges for real-time deployment: increased memory traffic, complex data layout transformations, and irregular memory access for RPE computation. To address these challenges, we present FASTR, the first FPGA accelerator for hierarchical transformer-based SAR foundation models. We introduce four key innovations: (1) a Hierarchical Multi-Purpose Buffer Architecture (HMBA) that reorganizes on-chip memory across stages without reallocation, (2) a data-layout transformation that enables implicit patch merging, (3) structured RPE bias integration that avoids irregular memory accesses, and (4) a Unified Processing Engine (UPE) that supports convolutions, linear projections, attention, and non-linear operations within a single compute core. We implement FASTR using high-level synthesis (HLS) targeting an AMD Xilinx defense-grade XQVU9P FPGA. Compared to CPU and GPU baselines, FASTR achieves 818× and 3× improvements in energy-delay product while delivering comparable latency to prior ViT accelerators despite processing a complex hierarchical Transformer architecture.
High-Level Synthesis (HLS) has democratised Field-Programmable Gate Array (FPGA) programming, yet Dynamic Partial Reconfiguration (DPR)—which enables runtime logic swapping for adaptive or oversized workloads—remains manual and expert-only. HiPR [1] adds limited compiler support but restricts modules to one-to-one region mappings without runtime management. MLIR-DPR introduces: (i) a dpr dialect in the Multi-Level Intermediate Representation (MLIR) infrastructure [2] for identifying mutually exclusive regions; (ii) automated interface synthesis, floorplanning, and multi-threaded scheduler generation; and (iii) demonstrated Software-Defined Radio (SDR), Design-Space Exploration (DSE), and virtual-area applications.
High-level synthesis allows users to express hardware designs in terms of software languages, raising the level of abstraction. However, most designers still prefer writing low-level RTL code. We present two classes of research works aiming to improve the appeal of HLS: (1) accelerators to showcase the power of HLS for ML applications, and (2) tools to improve the HLS developer experience.
Fully Homomorphic Encryption (FHE) enables privacy-preserving computation on encrypted data at a high computational cost. Among the existing schemes, CKKS is gaining traction thanks to its support for approximate arithmetic over real numbers. In such a scheme, the Number Theoretic Transform (NTT) is dominant, involving intensive modular arithmetic, twiddle-factor handling, and nontrivial memory access patterns. As a result, NTT acceleration has gained significant interest, with many FPGA designs achieving high throughput by aggressively exploiting device resources. While effective for NTT-centric workloads, this approach is ill-suited to full FHE pipelines, where the NTT must coexist with other compute-intensive kernels. Thus, we propose ReFHE-NTT, a resource-efficient NTT accelerator tailored to such settings. Our design combines on-the-fly twiddle-factor fusion with specialized modular arithmetic for pseudo-Mersenne primes, reducing memory footprint and arithmetic cost without storing precomputed tables. We co-design and validate the accelerator on the KV260 MPSoC, supporting polynomial degrees log N ∈ 12…16 and CKKS parameter sets with moduli up to 64 bits per prime. To the best of our knowledge, ReFHE-NTT is the first solution targeting embedded platform to support full-scale CKKS parameter sets. Compared to prior FPGA designs, it achieves up to a 20.2× improvement in slice-equivalent efficiency over the fastest open-source accelerator and a 1.98× improvement over the most resource-efficient one. Integrated into HEAAN CKKS library, ReFHE-NTT delivers top end-to-end speedup of 15× for encoding and 7.9× for encryption, demonstrating how resource-driven NTT design can substantially improve FHE performance on embedded platforms.
Dynamic graphs are ubiquitous in real-world scenarios, demanding both timely updates and low-latency responses. However, existing FPGA-based solutions still face three major limitations in supporting such workloads: • Heavy CPU dependence [3] • Inadequate support for dynamic graphs [1] , [2] • Poor support for irregular updates [4]
Mixed-precision and sparse machine-learning kernels increasingly stress CGRA interconnects because communicated values span byte- to word-scale precisions, while many CGRAs route fixed-width tokens under a uniform abstraction. This mismatch imposes a precision tax: narrow operands underutilize wide links, while wide values on narrow fabrics require fragmentation across multiple transfers. We present Fringe, a precision-aware CGRA communication substrate that treats precision as a first-class routing resource. Fringe exposes compiler-scheduled routing planes at different widths (8b and 32b data paths plus a 1b predicate path), enabling the mapper to allocate dependences onto precision-matched physical links without dynamic packing/unpacking hardware or loss of compile-time determinism. We prototype Fringe as a 4×4 mesh that separates narrow transport from widening-at-use for FP32 accumulation and quantify its implementation overhead in a GF12 ASIC synthesis flow. Relative to a precision-oblivious 32b-only baseline, Fringe increases total area by 1.81% and standard-cell area by 2.33%.
Vision-Language Models (VLMs) demonstrate remarkable capabilities in open-world understanding and interaction. However, edge deployment remains challenging due to strict constraints on power, latency, reliability, and privacy requirements. The VLM inference pipeline typically consists of three stages: visual encoding, cross-modal prefill, and autoregressive decoding. These stages exhibit distinct characteristics regarding operator types, parallel granularity, and memory access patterns. Consequently, a single homogeneous edge device (e.g., CPU, GPU, NPU, or FPGA) often fails to achieve simultaneous optimality in performance and energy efficiency across the entire pipeline.To address this, we propose a configurable FPGA–GPU heterogeneous collaborative system tailored for edge VLM inference. Leveraging specific hardware strengths, we map the compute-intensive visual encoding and cross-modal Prefill stages to the GPU, while offloading the bandwidth-sensitive autoregressive decode stage to the FPGA. This workload-aware mapping results in improved energy efficiency. To mitigate edge resource constraints, we designed a model compression method for edge GPUs and FPGAs. By compressing the model parameters to a range acceptable by the hardware and using only 5% of visual tokens, we achieved 88.9% of the baseline performance. On the FPGA, we implement a pipelined decoder that efficiently utilizes DDR bandwidth and propose an efficient deployment method for MoE (Mixture of Experts). Including aligned block layout of expert weights, operator fusion, and on-chip caching strategies to reduce bandwidth fluctuations caused by weight switching and improve throughput stability, enables the effective bandwidth utilization rate to reach 87.2%. Experimental results on a heterogeneous platform comprising a Jetson Orin Nano (8GB) and a Xilinx VU9P FPGA demonstrate an end-to-end inference throughput of 18.1 tokens/s. Compared to an NVIDIA RTX 4090 baseline, our system achieves a 2.67× improvement in energy efficiency.
High-level synthesis (HLS) design space exploration (DSE) aims to find Pareto-optimal designs but is hindered by slow synthesis evaluations. Existing graph neural network (GNN) surrogates struggle with homogeneous-style graph representations (causing signal over-squashing) and imprecise source-level heuristics for pragma mapping. We propose Chariot, an automated HLS optimization framework. Chariot leverages LLVM-based static analysis for high-fidelity Use-Def chain tracking, modeling HLS designs as semantic-rich heterogeneous graphs that explicitly map directives to true hardware targets. Our framework achieves state-of-the-art QoR prediction, identifying Pareto-optimal solutions with drastically reduced ranking regret while delivering orders-of-magnitude DSE speedup.
Routing is one of the most time-consuming stages in FPGA physical design and has a significant impact on overall QoR. While PathFinder has achieved great success, its sequential nature often limits global topology optimization, leading to redundant search efforts and inefficient utilization of routing resources. To address these limitations, this paper proposes a novel routing framework that enhances the router with global vision via precomputed Steiner potential fields. For each net, we construct a potential field from a Steiner-like topology, so that globally favorable trunk and junction regions are assigned higher potential. We then leverage this potential field to guide both net-level decisions and the subsequent search. First, we utilize the field to determine a topology-aware sink ordering policy that prioritizes sinks with high expected sharing benefits. Second, during the subsequent search, the field modulates the A* cost function to steer expansions toward high-potential Steiner junctions, thereby minimizing unproductive search space exploration. On Titan benchmarks, our approach reduces the minimum routable channel width by 1.35% on average compared with the VPR 9 baseline. For each circuit, when evaluated at the baseline VPR 9 minimum routable channel width, the proposed router reduces total wirelength by 1.60% and routing runtime by 18.94% on average. It also reduces heap push operations by 20.86% and heap pop operations by 26.84%, while preserving overall timing performance.
Deep neural networks (DNNs) have achieved remarkable success in various domains. However, their deployment on resource-constrained devices and in ultra-low-latency scenarios remains challenging due to their substantial computational and memory requirements. This paper proposes leveraging the low-dimensional computing (LDC) classifier, a low-dimensional variant of the vector symbolic architecture (VSA) classifier, as a lightweight alternative to DNNs. We introduce VSALUT, an open-source framework for implementing LDC on FPGAs. VSALUT employs a lookup table (LUT)-based architecture, an approximate encoding scheme to replace complex adders, a pruning strategy to reduce the model’s size, and a pipelining technique to maximize performance and resource efficiency. Evaluation on five datasets, commonly used to evaluate ultra-low latency architectures, demonstrates that VSALUT achieves significant hardware size and latency reductions over existing LDC, high-dimensional VSA, and LUT-based DNNs. This work establishes a promising new research direction for ultra-low-latency, lightweight inference on FPGAs using LDC.
Vision–Language–Action (VLA) models have demonstrated strong generalization across robotic tasks and embodiments. However, current deployments rely on GPU-based inference that is power inefficient for edge platforms, motivating the exploration of more efficient hardware targets. We present an initial exploration of the deployment of a VLA model on an AMD XDNA1 NPU, targeting SmolVLA and using Allo, a Python-based dataflow DSL. Operational intensity profiling identifies GEMM as the dominant kernel and the primary NPU target. To support SmolVLA’s wide dynamic shape variation, we develop a pre-cached profiling database augmented by an LLM-assisted tiling agent. Normalization and activation kernels are further optimized through vectorization and approximations. This work results in a functionally correct end-to-end prototype. As an initial exploration, we also discuss current limitations and optimization opportunities toward practical VLA deployment on NPUs.
High-Level Synthesis (HLS) improves hardware productivity by translating C/C++ programs into RTL implementations [1] . However, the quality of HLS designs strongly depends on pragma configurations such as loop pipelining, unrolling, and tiling. Since the pragma space is typically sparse, high-dimensional, and highly nonlinear, efficient design space exploration (DSE) remains challenging.
Task-level parallelism (TLP) is a long-standing approach in parallelizing control-dominated algorithms in software and has recently drawn interest in hardware acceleration thanks to the simplicity of managing tasks in hardware. Several TLP frameworks for FPGAs, like ParallelXL and HardCilk, leverage high-level synthesis to facilitate the acceleration of efficient TLP algorithms on FPGAs. In particular, HardCilk managed to efficiently deploy up to 256 processing elements (PEs) on a single FPGA system for microbenchmarks. However, for practical applications, it is usually not possible to fit more than a dozen PEs per FPGA, a limitation that reduces the potential of TLP. In this work, we propose an architecture that exploits the latency insensitivity of TLP and the high-bandwidth networking available in modern FPGAs to increase the number of available PEs for a given workload. We show that it is possible to span multiple FPGAs without loss of efficiency and with only a small resource overhead. We conduct experiments that distribute 128 PEs among two, four, and eight FPGAs and compare the efficiency with that of a single FPGA HardCilk system for a representative set of benchmarks. Our results accentuate the importance of an effective task movement policy across FPGAs to achieve scalability, particularly under specific network latency and bandwidth configurations. We also develop three real-world applications and test with two FPGAs setup, achieving almost perfect scalability. Our architecture achieves multi-FPGA extension with less than 3% of additional resource utilization.
The emergence of quantum computing poses significant threats to conventional cryptographic systems, necessitating the efficient hardware acceleration of Post-Quantum Cryptography (PQC), especially on the Field-Programmable Gate Array (FPGA) platforms. SPHINCS+, recently standardized by NIST (National Institute of Standards and Technology) as SLH-DSA (Stateless Hash-Based Digital Signature Algorithm), represents the only hash-based digital signature scheme. Its practical deployment, however, is restricted by computationally intense operations, particularly in the eXtended Merkle Signature Scheme (XMSS) tree, where WOTS+ (Winternitz One-Time Signature Plus) public key generation consumes the majority of signature generation cycles. With this background, this paper presents Trident, an innovative FPGA-based hardware accelerator that addresses critical performance and resource challenges in XMSS of SLH-DSA. First, we propose a triangle hash unit architecture that enables parallel execution of up to three hash operations simultaneously, directly addressing the computational bottleneck in XMSS tree construction and WOTS+ chain operations. Second, we develop an optimized memory caching scheme that reduces on-chip memory requirements via intermediate value management. Third, we implement the Trident on FPGAs and comprehensively evaluate it across all parameter sets at multiple security levels, i.e., up to 8.6× improvement in signature generation and up to 5.4× speed-up in verification operations. Extended Hypertree evaluation shows a 34.6× area-delay product (ADP) improvement on UltraScale+ FPGA for SLH-DSA-128s. This Trident represents a significant advancement toward practical SLH-DSA deployment in FPGA environments.
Attention is a major bottleneck when mapping Transformer-like models to FPGAs, as its matrix multiplications and normalisation stages exhibit differing numerical requirements and are highly sensitive to accumulation error. In this work, we propose operator-wise mixed-precision schemes and configurable accumulation strategies for attention-like pipelines based on shared-exponent low-bit, block floating-point style formats. By combining custom arithmetic with FPGA-specific design optimisations, our approach improves the trade-off between model quality and hardware cost, enabling more efficient deployment of small language models on reconfigurable hardware.
Transformer layers dominate the computational workload of transformer-based LLMs, creating a strong need for efficient transformer layer acceleration. The AI engine-based FPGA architecture offers the potential for significantly higher efficiency for transformer layer computing compared to conventional FPGAs. In this work, we present an integer linear programming-based approach, called LegoMap, which automatically maps the transformer layer onto AI engine-based FPGAs. Our method jointly optimizes AI engine core allocation, memory usage, and scheduling. Evaluated on the Versal ACAP, it delivers about 30% − 58% throughput improvement over the state-of-the-art automatic approach across different workloads.
Reinforcement learning (RL) enables autonomous decision-making in applications such as robotics and control, and Soft Actor-Critic (SAC) is a leading model-free algorithm for continuous tasks. However, SAC’s small-batch training updates and fine-grained computation lead to heavy scheduling and kernel-launch overheads on GPU, limiting efficiency. In this work, we present FHPSAC (FPGA-based High-Parallelism SAC Accelerator), the first FPGA-accelerated architecture dedicated to SAC training. First, we propose a hardware–software co-designed on-chip memory hierarchy to statically partition and allocate SAC’s training data for conflict-free parallel access. Second, we build a high-parallelism accelerator with a tensor core for GEMM (General Matrix Multiply) and a lightweight unit for irregular elementwise/reduction kernels. Finally, we implement the full system on a Xilinx XCVU9P FPGA and demonstrate significant speedup with low power. Experimental results show that FHPSAC obtains 5.33–14.85× speedup compared with the Intel Xeon Gold 6130 CPU, while outperforming an NVIDIA A100-SXM4 GPU by 2.90–10.43× in training latency with an average power of 40.17 W. FHPSAC substantially reduces SAC training latency, providing a computational foundation for large-scale SAC deployments.
Design space exploration (DSE) aims to search for the best design architecture for a given neural network on a target device. In this paper, we propose a DSE engine for FPGAs, considering multi-core layer-pipelined designs. Our main contributions include (1) an accurate model of resource usage and computation throughput for pipeline designs, (2) a DSE solver with consideration of both on-chip resource and off-chip memory bandwidth limitations for given FPGA boards and (3) a configurable computing core. The balance between computation throughput and data transmission for pipeline designs is considered in our DSE engine to achieve the best performance. Experimental results on ResNet-18 and VGG-16 demonstrate that our pipeline designs achieve 1.17×–4.41× performance improvements compared with state-of-the-art baselines. The results also show that group-based pipeline designs may outperform full pipeline designs due to limited off-chip memory bandwidth and on-chip memory resource.
This work introduces the Split-Posit format, designed to mimic the benefits of high-precision Posit values at significantly lower bit widths, achieving a favourable trade-off between accuracy and hardware efficiency. Furthermore, we propose a specialized digital signal processing (DSP) architecture for embedded FPGAs tailored for Split-Posit arithmetic, efficient and well-suited for its variable-length field structure.
