Register Transfer Level (RTL) code optimization is critical for meeting performance and power budgets in Field-Programmable Gate Array (FPGA) design. Traditional approaches depend on expert knowledge or heuristics, which are time-consuming and error-prone. Therefore, recent research has explored using Large Language Models (LLMs) for RTL code optimization and providing initial evidence of their potential. However, the capabilities and limitations of LLMs in RTL code optimization have not been systematically assessed, especially for RTL with complex timing logic. Moreover, these studies cannot distinguish whether improvements come from genuine reasoning or merely reproducing memorized patterns from training data. To address these problems, we present a metamorphic testing-based evaluation method and a companion benchmark to measure the effectiveness of LLM-aided RTL code optimization. Our key idea is that optimization effectiveness should be consistent across RTL descriptions that are semantically equivalent. We first build a benchmark suite covering four domains (logic operations, datapaths, timing control flow, and clock domains). We then apply domain-specific transformations to produce semantically equivalent RTL code with different code forms. We assess each method by applying it to both the original and the transformed code, synthesizing them with the same flow, and comparing the synthesis results. Through extensive experiments, our results show that LLM-aided methods effectively optimize logic operations and data paths, achieving lower or stable wire counts and area with delays near baseline. For timing control flow and clock domains, the gains are limited, and structural ratios often rise. Larger code size also increases the chance of incorrect rewrites, especially in timing and cross-domain designs. We further explore the application of prompt engineering include few shot examples and Chain-of-Thought (CoT), to improve RTL code optimization. Based on these results, we discuss practical directions and give concrete suggestions for using LLMs in RTL optimization.
This editorial introduces the articles in the FPL 2025 Journal Track. The articles address difficult problems across the FPGA computing stack, including CAD-flow debugging and design-space exploration, programmable-logic capacity and utilization, and scalable homomorphically encrypted matrix multiplication. Although the contributions operate at different abstraction levels, each pairs its central idea with the models, tools, architectural mechanisms, or algorithms needed to evaluate it. Together, they illustrate how coordinated advances across these levels can improve FPGA design productivity, hardware efficiency, and application performance.
Homomorphic Encryption (HE) enables secure computation on encrypted data, addressing privacy concerns in cloud computing. However, the high computational cost of HE operations, particularly matrix multiplication (MM), remains a major barrier to its practical deployment. Accelerating Homomorphic Encrypted MM (HE MM) is crucial for applications such as privacy-preserving machine learning. In this article, we present S \({}^{2}\) MM, the first scalable FPGA-based accelerator designed for HE MM. We show that HE MM is fundamentally bottlenecked by excessive off-chip memory traffic when operating with practical HE parameter sets. To analyze this bottleneck, we develop a cost model that characterizes the on-chip memory requirements of ciphertexts during HE MM, revealing the scalability limits of CPU-based implementations. Guided by the analysis, we propose a novel datapath for Homomorphic Linear Transformation (HLT), the dominant workload in HE MM. The proposed datapath enables fine-grained on-chip data reuse, substantially reducing both off-chip memory traffic and on-chip memory demand. To further improve scalability, S \({}^{2}\) MM supports tiled HE MM, removing the matrix size limitation imposed by the HE encoding capacity and enabling efficient computation on large matrices. In addition, the architecture is highly configurable, adapting to diverse matrix sizes and HE parameter sets while maximizing throughput within FPGA resource constraints. We also introduce a systematic configuration methodology to determine optimal design parameters for efficient deployment across varying workloads and platforms. We implement S \({}^{2}\) MM on an Alveo U280 and conduct comprehensive evaluations across a wide range of matrix sizes, shapes, and HE parameters. Experimental results demonstrate that S \({}^{2}\) MM achieves average speedups of 219 \(\times\) and 37.4 \(\times\) over state-of-the-art CPU and GPU implementations, respectively. We further evaluate S \({}^{2}\) MM in an application-level encrypted CNN inference pipeline, achieving a 6.08 \(\times\) end-to-end speedup by accelerating the HE MM-dominated fully connected layers.
Field-programmable gate arrays (FPGAs) have been an efficient alternative for the implementation of digital circuits. Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the LUT input number to improve performance and logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient logic architecture. Previous approaches primarily design dedicated hardware by analyzing the frequency distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this article, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT. Post-synthesis results on VTR and Koios benchmarks demonstrate that FLAIC reduces the logic levels by over 20% compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 11.9% and reduction in the number of Configurable Logic Blocks by 1.5% without sacrificing routability, compared to Intel Stratix 10-like architecture
Modern FPGA computer-aided design (CAD) flows have grown increasingly complex, integrating numerous stages, configuration parameters, timing constraints, and physical implementation specifications. As designs scale, failures often arise from subtle interactions across command-line options and constraint files, making debugging time-consuming and heavily dependent on expert knowledge. Identifying the root cause of such failures and determining the appropriate corrective action remains a major productivity bottleneck in CAD workflows. This article presents VTR-LLM , a fully automated, multi-agent framework for diagnosing and resolving failures in the Verilog-to-Routing (VTR) CAD flow. VTR-LLM leverages large language models (LLMs) in combination with retrieval-augmented generation (RAG) and specialized agents that target distinct sources of errors, including command-line invocations, timing constraints (i.e., Synopsys Design Constraints or SDC), and floorplanning specifications. A Classification Agent dynamically assigns each failure to the most appropriate agent and supports sequential resolution for compound failures involving multiple error sources. The system leverages LLMs without requiring fine-tuning, enabling the use of the latest models such as GPT-OSS-120B, by using RAG and intelligent agents to add domain-specific context and behaviors. We evaluate VTR-LLM using a dataset of 92 distinct VTR failure cases spanning multiple error patterns and levels of complexity. VTR-LLM can resolve 95% of all failures fully automatically, with robust performance across error categories. Additional studies demonstrate the impact of documentation retrieval scope, tool iteration, and LLM model choice on resolution accuracy and inference cost.
