Approximate multipliers (AMs) are widely explored to enhance the energy efficiency in convolutional neural network (CNN) applications. Unlike the manual design that usually results in a few AMs with dedicated error characteristics, approximate logic synthesis (ALS) can produce AMs automatically under specific constraints. However, the huge amount of time spent on evaluating numerous candidate AMs makes ALS less efficient. To address this, this work reveals the mathematical relationship between the mean error (ME) of an unsigned recursive multiplier and the MEs of its building blocks. As a result, the ALS task for a recursive multiplier can be decomposed into multiple independent ALS tasks for its building blocks. The ALS of building blocks is performed by modifying the values within the exact truth table using an evolutionary algorithm. Consequently, an AM synthesis framework is developed for achieving the Truth-table-level Approximation of Recursive Multipliers, denoted as TARM. TARM is used to synthesize unsigned 8×8 AMs for CNN applications, including VGG, ResNet, Inception, and MobileNet on CIFAR-10 or ImageNet dataset. Experimental results show that the error evaluation process within TARM is about 76× faster than that within a state-of-the-art ALS framework. Compared with the exact multiplier from DesignWare, the TARM-based AMs can reduce power by 10.3% to 13.3% and area by 7.0% to 15.9%, with a maximum accuracy loss of 0.16% in the corresponding AM-based CNN applications.
Lightweight mutual authentication protocols typically employ Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) as fundamental security primitives to protect device privacy. However, the dedicated circuitry of PUFs and TRNGs inevitably introduces prominent intermediate attack points. The concept of integrating PUF and TRNG functionalities into a shared entropy source has thus emerged as a new security paradigm. This paper presents a lightweight arbiter-based auto-calibration true random number generator (AAC TRNG) which harvests the entropy from a hardware-reused physically unclonable function (PUF). The proposed AAC TRNG can real-time evaluate the generated random data from the digitization & evaluation circuit (DEC), and then automatically maximize the entropy through configuration parameter optimization. Assessed using an arbiter-based (64,8)-OIPUF with Artix-7 FPGA, the proposed AAC TRNG only requires an additional hardware of 28 LUTs and 24 FFs. Benefited from the proposed auto-calibration mechanism, the proposed AAC TRNG attains an H∞ of 0.99989 while supporting a throughput of up to 25Mbps. Evaluated using NIST SP 800-90B, the minimum result of ten entropy estimators across four FPGA devices is up to 0.931665. The generated raw data can also pass all the NIST SP 800-22 and BSI AIS 31 statistical tests even under temperature variations from -20°C ∼ 80°C. This work also achieves a Figure of Merit (FoM) of 4.77, outperforming prior arts.
This preface is an introduction to the Embedded Systems Week (ESWeek) 2026 Special Issue. ESWeek is a premier international forum for research and innovation in embedded systems, bringing together researchers, practitioners, and students working across the increasingly interconnected areas of embedded computing, real-time systems, cyber-physical systems, and design automation. Modern embedded systems are becoming more complex and heterogeneous, integrating multicore and manycore processors, specialized accelerators, machine learning, distributed computing, and networked sensing and actuation under stringent requirements for timing, energy efficiency, reliability, safety, and security. These systems increasingly operate in dynamic and uncertain environments, making it essential to reason about their behavior across multiple levels of abstraction, from hardware and architecture to operating systems, software, networks, and applications. Emerging technologies such as artificial intelligence, autonomous systems, edge computing, and advanced communication networks further challenge traditional design and verification methodologies, while demanding new approaches for managing resource constraints, timing requirements, concurrency, and system-level interactions. Addressing these challenges requires integrated methodologies that combine modeling, analysis, synthesis, optimization, verification, and learning to enable the efficient development of trustworthy embedded systems. ESWeek provides a unique venue for advancing these methodologies and for fostering interaction among traditionally distinct embedded-systems communities.
Modern multi-FPGA platforms increasingly employ multi-die integration to scale logic capacity whereas inter-die communication remains constrained by limited physical I/O. Time-division multiplexing (TDM) mitigates this bottleneck by sharing wires across multiple signals; however, aggressive TDM ratios can substantially increase serialization latency and worsen critical connection delay. In this paper, we propose a comprehensive algorithmic framework for die-level routing and TDM optimization in multi-FPGA systems to jointly manage routability and timing. We first present a delay-constrained rerouting algorithm that improves timing while controlling routing-resource usage by enforcing connection-level delay bounds and promoting edge reuse. Next, we formulate TDM ratio assignment as a block-angular convex optimization problem and solve it using Lagrangian decomposition, providing a (1 + ϵ)-approximation guarantee for any ϵ > 0. Finally, we introduce a delay-aware TDM wire assignment method that maps signals to physical wires while minimizing the incremental delay induced by ratio adjustments. Experiments on standard benchmarks show consistent improvements over state-of-the-art techniques: under a fixed routing method, our TDM optimization alone reduces normalized critical connection delay by 10.8%, and combining it with delay-constrained rerouting achieves a 16.5% reduction.
Module-Lattice Key Encapsulation Mechanism (ML-KEM) has been standardised by NIST as the primary key establishment algorithm for Post-Quantum Cryptography (PQC). Despite the proven mathematical security of the underlying algorithm, its implementation can be vulnerable to active fault injection attacks, which may allow the recovery of the secret key. This work proposes a fault detection architecture for the most time-consuming operation of ML-KEM, i.e., the polynomial multiplication. The architecture is based on the Redundant Residue Number System (RRNS) and is applied to the number-theoretic transform (NTT)- based polynomial multiplication of ML-KEM. The proposed method can detect single faults in RRNS residues with 100% error coverage and multiple errors with 96.97 % coverage. The proposed design was evaluated on a Xilinx Artix-7 FPGA, and the results show minimal area and time overhead.
