Near-bank Processing-in-Memory (PIM) architectures integrate processing cores (PIMcores) close to DRAM banks to mitigate the high cost of off-chip memory accesses. However, when accelerating CNNs on DRAM-PIM with conventional layer-by-layer dataflow, cross-bank dependencies between consecutive layers necessitate the reorganization of inter-layer activations and their transfer across banks before executing the next layer. To address this challenge, we propose PIMfused, a hardware–software co-design that exploits fused-layer dataflow for end-to-end CNN execution on DRAM-PIM. PIMfused reformulates fused-layer execution under the PIM memory hierarchy and bank-level execution constraints. On the software side, the fused-layer dataflow eliminates inter-layer activation dependencies across banks, improving activation movement efficiency while preserving bank-level parallelism. As fusion depth increases, PIMfused shifts activation movement from cross-bank transfers to local bank accesses. On the hardware side, PIMfused extends AiM-based architecture with lightweight PIMcore support for fused-layer execution and small local buffers (e.g., 64B) to enable intra-layer data reuse. Due to the strict area constraints of DRAM-PIM, inter-layer activations are retained in DRAM banks instead of being fully buffered on chip as in conventional CNN accelerators. We further develop a PPA (performance–power–area) profiling framework to analyze design trade-offs across ResNet18, VGG19, and MobileNetV2, from which we derive five key insights. We show that PIMfused outperforms the layer-by-layer baseline by improving data movement efficiency while requiring only small buffer resources.
The Logical Execution Time (LET) paradigm is a clean abstraction that decouples functional semantics from implementation details in real-time control systems. However, practical experience shows that strictly enforcing LET semantics is often unrealistic: execution on embedded platforms is subject to variability, communication delays, and hardware contention. This makes exact LET adherence costly or even impossible. In this work, we propose to relax the strict deterministic analysis and instead study a probabilistic model that captures the essence of LET implementations without requiring full conformance. By allowing read and write instants to vary within given probability distributions, the probabilistic LET (pLET) framework maintains the conceptual benefits of LET while reflecting the timing uncertainty of real systems. Our analysis uses a probabilistic model for data propagation through a directed acyclic graph (DAG) of periodic tasks. We use the model to quantify the impact of implementation-related considerations on the performance of the closed-loop system. We apply the analysis to an example case study and to a model of a Crazyflie drone, showing that the pLET analysis allows us to give system-level guarantees and can help refine real-time parameters such as task periods.
Privacy boundaries among intellectual property (IP) vendors make conventional centralized Network-on-Chip (NoC) mapping difficult to apply to heterogeneous chiplet-based DSP platforms. The problem is further complicated by non-independent and identically distributed (non-IID) design preferences, strict bandwidth and timing constraints, and the large discrete search space arising from energy-latency trade-offs. This paper presents FedMap, a federated deep reinforcement learning approach that separates centralized environment simulation from decentralized policy optimization. Under a trusted-coordinator threat model, participating vendors retain proprietary communication graphs, task information, and traffic characteristics locally, while model updates are protected through gradient clipping, local noise perturbation, and secure aggregation. To improve mapping efficiency, FedMap incorporates a preference-conditioned graph hierarchical Actor-Critic (PC-GAC), which exploits communication dependencies and decomposes the original decision space while adapting to different energy-latency preferences. In addition, a preference-clustered, contribution-aware aggregation strategy (PC²-Agg) is developed to mitigate instability caused by heterogeneous client objectives and constraint conditions. Evaluations on real-time heterogeneous DSP mapping tasks show that FedMap consistently achieves better solutions than representative state-of-the-art approaches. It decreases communication cost, communication energy, and average network latency by 40.95%, 41.38%, and 39.10%, respectively. The framework also maintains stable mapping performance as system scale increases and constraints become more stringent, demonstrating its potential for privacy-preserving collaborative NoC optimization.
The Cosine Number Transform (CNT) has been widely used for medical image encryption for Digital Imaging and Communications in Medicine (DICOM) formats. Most existing medical encryption algorithms primarily focus on 8-bit-depth DICOM images. While shorter transforms (e.g., 8-point) suffice for lightweight tasks, a 16-point Fast Cosine Number Transform (FCNT) is more suitable for high-fidelity signal processing, due to its advantages in spectral resolution, computational efficiency, and noise robustness. The traditional 16-point FCNT exhibits data dependency in the odd rows of its transformation matrix, which imposes constraints on hardware circuit parallelization and lightweight design implementation. To address these challenges, a Configurable 16-point Fast Cosine Number Transform (CCNT-16) algorithm is proposed for high-bit-depth DICOM images. We implement the algorithm in hardware on FPGA platform. Compared with existing methods, the CCNT-16 circuit achieves a 19.7% reduction in Look-Up Table (LUT) usage, a 13.2% decrease in Flip-Flop (FF) consumption, and an 81.5% reduction in computational latency. The configurable DICOM image encryption/decryption hardware accelerator proposed in this work achieves encryption and decryption of 512×512 DICOM-formatted Computed Tomography (CT) images within 0.96 ms, meeting the real-time processing requirements for telemedicine applications. The source code of this work is available at https://github.com/netflymachine/CCNT-16.
Embedded and edge platforms increasingly run safety- or mission-critical workloads, yet tight power and area budgets limit continuous security monitoring. Although traditional anomaly detectors can achieve high accuracy, they often require resource-intensive computations impractical for constrained deployments. To address these limitations, we propose RadScan, a hardware-assisted runtime anomaly detection framework that monitors a single power trace using an electric double layer transistor (EDLT)-based physical reservoir computing system to nonlinearly map the signal into a high-dimensional reservoir state. This analog front end reduces digital processing and provides greater energy and area efficiency than traditional digital CMOS detectors. RadScan is evaluated using reservoir states generated by a physics-based COMSOL EDLT model driven by power traces measured from an STM32F303RC (ARM Cortex-M4) executing PARSEC benchmarks. Under controlled workload substitution, RadScan achieves 98.08% accuracy in the single-benign setting with a detection latency of 73 samples and 96.27% in the multi-benign setting. For malware-oriented anomalies, injected code-injection and code-reuse segments yield 95.8-98.3% detection accuracy across workloads. Post-layout, system-level RadScan consumes 81.641 μW and occupies 7684.11 μm2, enabling continuous monitoring on resource-constrained devices. Overall, RadScan provides higher energy efficiency and moderate area efficiency while maintaining high accuracy across attack vectors, making it suitable for battery-powered remote sensing nodes and field-deployed IoT endpoints in untrusted environments.
