This paper provides an overview of the domain challenges, use cases, objectives, high-level concepts, intended innovations, and expected impact of the DistriMuSe project. The project’s main aim is to enhance human health and safety by improved sensing of human presence, behaviour, intentions and vital signs in a collaborative or common environment by means of multi-sensor systems, distributed processing and machine learning. The use cases address challenges in health monitoring of elderly, sleep and exercise, of drivers and vulnerable road users in traffic and of people interacting with robots in a factory environment. Technical development in the project focuses on unobtrusive monitoring sensors, multi-sensor systems, distribution of computation and intelligence, and domain specific needs for the use cases.
Current heterogeneous systems integrate general-purpose Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs). The efficient use of such systems requires a significant programming effort to distribute computation and synchronize across devices, which usually involves using Atomic Memory Operations (AMOs). Arm recently launched a floating-point Atomic Memory Operations (FAMOs) extension to perform atomic updates on floating-point data types specifically. This work characterizes and models heterogeneous architectures to understand how floating-point AMOs impact graph, Machine Learning (ML), and high-performance computing (HPC) workloads. Our analysis shows that many AMOs are performed on floating-point data, which modern systems execute using inefficient compare-and-swap (CAS) constructs. Therefore, replacing CAS-based constructs with FAMOs can improve a wide range of workloads. Moreover, we analyze the trade-offs of executing FAMOs at different memory hierarchy levels, either in private caches (near) or remotely in shared caches (far). We have extended the widely used AMBA CHI protocol to evaluate such FAMO support on a simulated chiplet-based heterogeneous architecture. While near FAMOs achieve an average 1.34x speed-up, far FAMOs reach an average 1.58x speed-up. We conclude that FAMOs can bridge the gap between CPU architecture and accelerators and enabling synchronization in key application domains.
E0 encryption is primarily used in Bluetooth devices to ensure secure communication, and it is also integrated into various IoT devices for secure data transmission. Small-scale variants of E0 are explored for optimizing performance and security in devices with limited computational resources. This study explores the algebraic cryptanalysis of small-scale variants of the E0 stream cipher, a legacy cipher used in the Bluetooth protocol. By systematically reducing the size of the linear feedback shift registers (LFSRs) while preserving the cipher's core structure, we investigate the relationship between the number of unknowns and the number of consecutive keystream bits required to recover the internal states of the LFSRs. Our work demonstrates an approximately linear relationship between the number of consecutive keystream bits and the size of small-scale E0 variants, as indicated by our experimental results. To this end, we utilize two approaches: the computation of Grobner bases using Magma's F4 algorithm and the application of CryptoMiniSat's SAT solver. Our experimental results show that increasing the number of keystream bits significantly improves computational efficiency, with the F4 algorithm achieving a speedup of up to 733x when additional equations are supplied. Furthermore, we verify the non-existence of equations of degree four or lower for up to seven consecutive keystream bits, and the non-existence of equations of degree three or lower for up to eight consecutive keystream bits, extending prior results on the algebraic properties of E0.
NET4EXA aims to develop a next-generation high-performance interconnect for HPC and AI systems, addressing the increasing demands of large-scale infrastructures, such as those required for training Large Language Models. Building upon the proven BXI (Bull eXascale Interconnect) European technology used in TOP15 supercomputers, NET4EXA will deliver the new BXI release, BXIv3, a complete hardware and software interconnect solution, including switch and network interface components. The project will integrate a fully functional pilot system at TRL 8, ready for deployment into upcoming exascale and post-exascale systems from 2025 onward. Leveraging prior research from European initiatives like RED-SEA, the previous achievements of consortium partners and over 20 years of expertise from BULL, NET4EXA also lays the groundwork for the future generation of BXI, BXIv4, providing analysis and preliminary design. The project will use a hybrid development and co-design approach, combining commercial switch technology with custom IP and FPGA-based NICs. Performances of NET4EXA BXIv3 interconnect will be evaluated using a broad portfolio of benchmarks, scientific scalable applications, and AI workloads.
Multicore platforms are complex systems where resources are shared among different processing entities, making it difficult to study their behavior in a deterministic way, which is vital in safety-critical systems. One of the most complex units on the processing cores of a multicore platform is the Memory Management Unit (MMU). The MMU efficiently manages the memory through the paging technique which consists in dividing virtual and physical memory into different fixed-size blocks called pages, mapping virtual addresses to physical ones, and sets the properties of the data within the page. This translation mechanism is ensured by considering different elements: (1) page translation tables, (2) table page descriptors and (3) other configuration registers which indicate the granularity and size of the pages, and the initial look-up level of the translation level. All this has an impact on the execution performance and, most importantly, on the execution determinism. Therefore, this work aims to analyze the aforementioned elements on a modern MMU (ARMv8) in order to understand their impact on the core itself and other concurrently executing cores of a multicore platform.
Vision impairment increases risks such as social isolation, mobility challenges, and falls. Wearable Augmented Reality (AR) devices with Artificial Intelligence (AI) can enhance sensory perception by enabling real-time recognition of obstacles, assisting visually impaired individuals during street navigation, aiming to reduce the risk of falls. In this paper, we propose a Federated Learning (FL) framework for outdoor obstacle detection using resource-constrained edge AR devices. As such, our proposed framework is designed to optimize energy efficiency by partially fine-tuning a generic pre-trained model originally developed for visually impaired assistance. Our framework is evaluated on a testbed with NVIDIA Jetson Nano, demonstrating that FL improves accuracy over standalone models on each AR device, while achieving an accuracy comparable to centralized approaches, but without the need to transfer the local raw data on each AR device to a central server/cloud to alleviate privacy concerns.
ASTRAEUS project aims to improve the use of Commercial-Off-The-Shelf (COTS) devices in space telecommunication applications. The goal is to develop specialized radiation mitigation techniques for both hardware and software components with a special focus on the latter. The aim is to demonstrate the feasibility and reliability of these techniques, enabling their future use in telecommunication payload processing units. The SIHFT (Software Implemented Hardware Fault Tolerance) approach will be enforced, where some proper modification to a conventional compilation toolchain, will make possible the identification of temporary fault and the adoption of fault tolerant solutions. The successful implementation of this project will de-risk the use of software-based radiation mitigation techniques and foster the adoption of high-performance while cost-effective COTS electronics in space applications.
ORB-SLAM3 is a state-of-the-art visual SLAM system, but its computational complexity poses major challenges for real-time deployment on embedded platforms. While prior work has largely focused on accelerating front-end tasks like feature extraction, back-end stages such as bundle adjustment remain less explored due to their algorithmic complexity and memory-intensive nature. Furthermore, most existing solutions accelerate specific modules without integrating them into a complete SLAM framework. In this work, we present SoC-SLAM, a novel FPGA-based hardware/software co-design that accelerates both the front-end and back-end stages of ORB-SLAM3 within a unified framework. Profiling identifies ORB feature extraction and local bundle adjustment as the primary performance bottlenecks, both critical for maintaining real-time system responsiveness. To address these, we develop modular FPGA-based accelerators for ORB extraction and key bundle adjustment solver steps, including Schur elimination, Cholesky decomposition, and back substitution, while retaining the remaining pipeline in software. Since the workload predominantly consists of operations on sparse block matrices, we develop and combine several optimization techniques, including matrix partitioning and pipelined block processing, to efficiently handle sparsity and maximize parallelism. Evaluation on the EuRoC MAV dataset shows 8x and 7.4x speedups for ORB extraction and local bundle adjustment, resulting in 2.4x and 3.3x improvements in the Tracking and Local Mapping threads, respectively. The system operates at 222 MHz, consumes 4.276W, and achieves an RMSE of 0.02832 m. Our fully integrated pipeline demonstrates competitive performance and power efficiency compared to prior FPGA, ASIC, and GPU-based solutions. The proposed architecture is scalable and generalizable to other bundle adjustment modules, such as global bundle adjustment, welding bundle adjustment, and essential graph optimization, offering an extensible hardware acceleration design for real-time visual SLAM on resource-constrained platforms.
Cryptography and data security are a main concern on the current digital communication world, but authenticated encryption (AE) protocols have been under performing. The CAESAR competition provided the opportunity for new proposals and discussions, that now reached the finalist stage with the AEGIS-128 and -256 authenticated ciphers. The work herein proposed takes into account the AEGIS implementation on FPGAs considering architectural trade-offs towards compact, efficient, and flexible implementations. A variation of the proposed solution also allows for the computation of both AEGIS and AES. This work considers a round-rolled 5/6-folded structure capable of processing both AEGIS-128 and -256 seamlessly, by carefully scheduling the 5 to 6 128-bit sub-states of the cipher. Experimental results suggest a maximum throughput of 5.9 and 4.9 Gbps for AEGIS-128 and AEGIS-256, respectively, on an AMD/Xilinx Zynq-7020. Furthermore, even though this design can process both AEGIS-128 and -256 variants (the first in the state-of-the-art) its occupation of only 496 Slices, makes it the most compact (and one of the most efficient) solutions on FPGAs, requiring 31.7% less resources than the smallest AEGIS-128 exclusive competitor. This is achieved with a cost of 16.6% less efficiency than the most efficient AEGIS-128 only design.
This work presents an efficient hardware architecture for hyperspectral image rotation, based on a geometric matrix transformation combined with bilinear interpolation to enhance pixel accuracy. These operations are commonly used in hyperspectral image (HSI) registration processes to compensate for motion in the observed scene. The primary objective of this research is to minimize the computational resource usage of the algorithm while optimizing overall efficiency. To achieve this, a reconfigurable hardware architecture based on FPGA is employed, where the rotation algorithm is implemented as an accelerator using the Vitis HLS synthesis tool and the block flow mechanism. The FPGA-based solution with four cores achieved a latency of 0,445 ms and a throughput of 1396,9 MB/s, with an energy consumption of only 1,09 mJ. Additionally, an alternative implementation was carried out on a GPU-based architecture (Jetson Nano), resulting in a higher latency of 12,55 ms and an energy consumption of 62,75 mJ. The evaluation included energy consumption, comparison with other solutions reported in the literature, and quality metrics. The results demonstrate that the FPGA-based solution is more efficient in terms of resource utilization and energy consumption, with minimal error.
Artificial Intelligence (AI) has traditionally prioritized high performance over compliance with functional safety standards such as IEC 61508. However, when AI systems are used in safety-related functions, it is essential to demonstrate that errors will not lead to malfunctions. This involves preventing systematic design-time errors and detecting and controlling runtime faults, as specified in IEC 61508. Moreover, ISO/PAS 8800 requires analyzing AI-specific development tools to identify and mitigate potential risks. In this paper, we take a step toward a safe end-to-end AI framework by focusing on systematic error avoidance in the implementation of You Only Look Once (YOLO), a widely used object detection model. A C-based version of YOLO-built on the Darknet framework-is analyzed using the Polyspace static analysis tool to assess MISRA C compliance. We apply corrective actions to eliminate violations, producing a MISRA C-compliant implementation. In addition, we propose a runtime error detection mechanism using dual execution on a diverse platform and validate behavioral consistency using the COCO dataset. This approach supports the development of trustworthy AI systems by addressing both systematic errors and runtime detection.
Cryptographic algorithms are indispensable from today's world and often require high-throughput implementations accelerated by specialized hardware like field programmable gate arrays (FPGAs). However, these implementations are vulnerable to passive and active side-channel attacks. This paper presents a clock glitch generator designed to inject precise glitches into a clock signal, enabling an active side-channel attack. The generator uses only FPGA clocking resources to maintain signal integrity. An FPGA-internal calibration method is incorporated to generate consistent glitches, independent of the implementation run and the physical device characteristics. The start and width of the glitches can be set with a step size of 0.53 degrees, equal to 14.8 ps, for a 100MHz clock. The generator's architecture allows glitches to be inserted in the positive and negative phase of the clock. This increases the versatility of possible attacks. The clock glitch generator was used to attack both the mixed-mode clock manager (MMCM) and phase-locked loop (PLL) primitives within the 7-Series and Ultrascale+ FPGAs from AMD-Xilinx. Despite the PLL's ability to filter out clock glitches, an attack scenario was successfully identified that stealthily increased the output frequency of a 7-Series MMCM and PLL by up to 68%.
Microarchitectural side-channel attacks are a growing concern and have been widely studied on x86 and ARM architectures, but RISC-V’s susceptibility to similar attacks remains understudied. We present the first implementation and evaluation of the Evict+Spec+Time attack on RISC-V, previously demonstrated only on x86 [2]. This advanced variant of Evict+Time integrates three critical phases: eviction, speculation, and timing. First, the attack forcibly evicts target cache lines using RISC-V’s cbo.flush instruction via the Zicbom extension [6]. Next, it exploits out-of-order execution to manipulate microarchitectural resources such as the reorder buffer, limiting the processor’s ability to mask cache-miss latency. Finally, it infers secret-dependent memory access patterns through precise timing measurements. We validate RISC-V’s vulnerability by recovering secret keys from AES T-table implementations. Using the gem5 simulator [4], we provide the first detailed analysis of microarchitectural behavior during the attack, including cache contention, pipeline stalls, and latency variations. These insights establish foundational guidance for developing RISC-V-specific countermeasures against such attacks.
ShapeFuture will drive innovation in fundamental Electronic Components and Systems (ECS) that are essential for robust, powerful, fail-operational and integrated perception, cognition, AI-enabled decision making, resilient automation and computing, as well as communications, for highly automated vehicles. The overarching vision of ShapeFuture is to bring ECS Innovation to the heart of Europe’s Mobility Transformation, thereby elevating sovereignty by perfecting programmable ECS solutions for intelligent, safe, connected, and highly automated vehicles. In this paper, we detail not only the vision and mission of the ShapeFuture project, but we also showcase the results achieved during the first year.
The European Defence Agency’s revised Capability Development Plan (CDP) identifies as a priority improving ground combat capabilities by enhancing soldiers’ equipment for better protection. The CAPSARII project proposes an innovative wearable system and Internet of Battlefield Things (IoBT) framework to monitor soldiers’ physiological and psychological status, aiding tactical decisions and medical support. The CAPSARII system will enhance situational awareness and operational effectiveness by monitoring physiological, movement and environmental parameters, providing real-time tactical decision support through AI models deployed on edge nodes and enable data analysis and comparative studies via cloud-based analytics. CAPSARII also aims at improving usability through smart textile integration, longer battery life, reducing energy consumption through software and hardware optimizations, and address security concerns with efficient encryption and strong authentication methods. This innovative approach aims to transform military operations by providing a robust, data-driven decision support tool.
This paper describes the NextPerception project’s outcomes organized as examples motivated by user stories. The project developed next-generation perception sensors and enhanced the distributed intelligence paradigm to build versatile, secure, reliable and proactive human monitoring systems, in turn applied in use cases in health and automotive domains.
The relevance of heterogeneous architectures has significantly increased over the last decade due to stagnation of performance scaling. Concurrently, increased performance-energy tradeoff requirements driven by the growth of edge computing, with a large focus on Artificial Intelligence (AI) inference, further motivates efforts towards hardware customization. In this context, the open RISC-V Instruction Set Architecture (ISA) and its custom extension oriented paradigm are a relevant technology towards this specialization. However, customizing a processor is a lengthy process requiring Hardware Description Language (HDL) expertise. Furthermore, for validation and simulation purposes, implementing an Instruction Set Simulator (ISS) of the modified core may also be a necessity. This introduces the need for development of two unrelated codebases, increasing development time and effort. In this paper, we explore High-Level-Synthesis (HLS) to realize both the hardware and the respective simulator through a single codebase, which reduces design effort and simplifies specialization of a RISC-V through specification of custom instructions at high level. We present a C++ based design of a RISC-V core, and validate it as an ISS, as well as a hardware module synthesized for an AMD Zynq UltraScale+ Field Programmable Gate Array (FPGA) through HLS, which we integrated in a System-on-Chip (SoC), and functionally validated through a state-of-the-art set of unit tests.
This paper presents a novel approach to formal modeling and analyzing the resilience of networked sensor and actuator systems against targeted cyber-attacks, leveraging Timed Process Algebra (TPA). Recognizing the critical role of these systems in modern infrastructures and their inherent vulnerabilities, we develop a formal TPA-based model to represent sensors, actuators, communication channels, and malicious intruders as interacting processes. This model captures the dynamic behavior of the network, including data flow, control commands, and timing constraints, enabling the analysis of attack scenarios such as sensor disabling, actuator compromise, and communication disruption. We demonstrate some decidable and undecidable properties regarding the precise modeling of intruders, as well as employ model checking and an equivalence approach to verify some safety properties concerning intruders and supervisors.
Microcontroller (MCU) performance screening ensures that devices meet critical specifications, such as maximum operating frequency (F-max). On-chip Speed Monitors (SMONs), implemented as ring oscillators, provide process-correlated signals that can be used to estimate F-max via machine learning (ML). However, traditional ML models require substantial domain expertise, extensive feature engineering, hyperparameter tuning, and dataset-specific training, limiting their scalability and generalization. In this preliminary study, we explore the use of TabPFN, a pretrained Tabular Foundation Model (TabFM) based on In-Context Learning (ICL), for MCU performance prediction. TabPFN eliminates the need for task-specific training or tuning by conditioning directly on labeled examples provided at inference time, enabling few-shot and zero-shot learning. We evaluate TabPFN on two distinct MCU datasets and compare its performance with conventional ML models, including tree-based and linear approaches. Our results show that TabPFN consistently achieves competitive accuracy with minimal human supervision, demonstrating its potential as a fast, generalizable, and low-maintenance alternative for performance screening in semiconductor manufacturing.
HQC is a quantum-resistant cryptographic key encapsulation mechanism, recently selected by NIST as a future standard. Polynomial multiplication is one of the most critical operations in HQC. Due to side-channel security concerns, the previously-used sparse-dense method was recently replaced by classical dense-dense multiplication implemented using Karatsuba's algorithm. This change has made polynomial multiplication the primary performance bottleneck, accounting for approximately 95% of the total execution time. This paper presents an alternative polynomial multiplication technique for HQC: the Frobenius Additive Fast Fourier Transform (FAFFT), which provides significant algorithmic-level performance improvements. We also present ANDROMEDA, the first state-ofthe-art hardware implementation of FAFFT, and evaluate its performance impact by integrating our solution in a resource-constrained RISC-V-based System-on-Chip scenario. Experimental results show that our solution improves HQC performance by approximately 9.64x and 19.22x across its security levels, making HQC more practical for real-world deployment.
