This paper provides an overview of the domain challenges, use cases, objectives, high-level concepts, intended innovations, and expected impact of the DistriMuSe project. The project’s main aim is to enhance human health and safety by improved sensing of human presence, behaviour, intentions and vital signs in a collaborative or common environment by means of multi-sensor systems, distributed processing and machine learning. The use cases address challenges in health monitoring of elderly, sleep and exercise, of drivers and vulnerable road users in traffic and of people interacting with robots in a factory environment. Technical development in the project focuses on unobtrusive monitoring sensors, multi-sensor systems, distribution of computation and intelligence, and domain specific needs for the use cases.
Current heterogeneous systems integrate general-purpose Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs). The efficient use of such systems requires a significant programming effort to distribute computation and synchronize across devices, which usually involves using Atomic Memory Operations (AMOs). Arm recently launched a floating-point Atomic Memory Operations (FAMOs) extension to perform atomic updates on floating-point data types specifically. This work characterizes and models heterogeneous architectures to understand how floating-point AMOs impact graph, Machine Learning (ML), and high-performance computing (HPC) workloads. Our analysis shows that many AMOs are performed on floating-point data, which modern systems execute using inefficient compare-and-swap (CAS) constructs. Therefore, replacing CAS-based constructs with FAMOs can improve a wide range of workloads. Moreover, we analyze the trade-offs of executing FAMOs at different memory hierarchy levels, either in private caches (near) or remotely in shared caches (far). We have extended the widely used AMBA CHI protocol to evaluate such FAMO support on a simulated chiplet-based heterogeneous architecture. While near FAMOs achieve an average 1.34x speed-up, far FAMOs reach an average 1.58x speed-up. We conclude that FAMOs can bridge the gap between CPU architecture and accelerators and enabling synchronization in key application domains.
E0 encryption is primarily used in Bluetooth devices to ensure secure communication, and it is also integrated into various IoT devices for secure data transmission. Small-scale variants of E0 are explored for optimizing performance and security in devices with limited computational resources. This study explores the algebraic cryptanalysis of small-scale variants of the E0 stream cipher, a legacy cipher used in the Bluetooth protocol. By systematically reducing the size of the linear feedback shift registers (LFSRs) while preserving the cipher's core structure, we investigate the relationship between the number of unknowns and the number of consecutive keystream bits required to recover the internal states of the LFSRs. Our work demonstrates an approximately linear relationship between the number of consecutive keystream bits and the size of small-scale E0 variants, as indicated by our experimental results. To this end, we utilize two approaches: the computation of Grobner bases using Magma's F4 algorithm and the application of CryptoMiniSat's SAT solver. Our experimental results show that increasing the number of keystream bits significantly improves computational efficiency, with the F4 algorithm achieving a speedup of up to 733x when additional equations are supplied. Furthermore, we verify the non-existence of equations of degree four or lower for up to seven consecutive keystream bits, and the non-existence of equations of degree three or lower for up to eight consecutive keystream bits, extending prior results on the algebraic properties of E0.
NET4EXA aims to develop a next-generation high-performance interconnect for HPC and AI systems, addressing the increasing demands of large-scale infrastructures, such as those required for training Large Language Models. Building upon the proven BXI (Bull eXascale Interconnect) European technology used in TOP15 supercomputers, NET4EXA will deliver the new BXI release, BXIv3, a complete hardware and software interconnect solution, including switch and network interface components. The project will integrate a fully functional pilot system at TRL 8, ready for deployment into upcoming exascale and post-exascale systems from 2025 onward. Leveraging prior research from European initiatives like RED-SEA, the previous achievements of consortium partners and over 20 years of expertise from BULL, NET4EXA also lays the groundwork for the future generation of BXI, BXIv4, providing analysis and preliminary design. The project will use a hybrid development and co-design approach, combining commercial switch technology with custom IP and FPGA-based NICs. Performances of NET4EXA BXIv3 interconnect will be evaluated using a broad portfolio of benchmarks, scientific scalable applications, and AI workloads.
Multicore platforms are complex systems where resources are shared among different processing entities, making it difficult to study their behavior in a deterministic way, which is vital in safety-critical systems. One of the most complex units on the processing cores of a multicore platform is the Memory Management Unit (MMU). The MMU efficiently manages the memory through the paging technique which consists in dividing virtual and physical memory into different fixed-size blocks called pages, mapping virtual addresses to physical ones, and sets the properties of the data within the page. This translation mechanism is ensured by considering different elements: (1) page translation tables, (2) table page descriptors and (3) other configuration registers which indicate the granularity and size of the pages, and the initial look-up level of the translation level. All this has an impact on the execution performance and, most importantly, on the execution determinism. Therefore, this work aims to analyze the aforementioned elements on a modern MMU (ARMv8) in order to understand their impact on the core itself and other concurrently executing cores of a multicore platform.
