This paper proposes a HW/SW Co-Optimized OnLine 3D Gaussian Splatting modeling accelerator, COOL-splat, for real-time AR/VR applications on mobile devices. To address high external memory access energy and redundancies in computation, COOL-splat introduces novel contributions across SW, core, and PE levels. Projected gradient interpolation-based masked training (SW), bi-directional rendering core (Core), and reconfigurable gaussian computation units supporting mixed-precision (PE). These enhancements achieve an average modeling efficiency of 10.1 mJ/iter, outperforming state-of-the-art processors by 1.49×.
This paper presents a multicore FPGA-based hardware accelerator for RLWE encryption and decryption using the TFHE scheme. The proposed modular architecture consists of two main components, namely the encryption and decryption units, each implemented with up to four parallel RTL cores. The implementation on an Xilinx ZCU104 FPGA operates at maximum frequencies of 214 MHz for encryption and 300 MHz for decryption, supporting polynomial degrees up to 4096. The proposed design achieves throughputs of 9.07 Gbps and 12.73 Gbps for encryption and decryption, respectively. (Keywords: TFHE, RLWE, Multicore, Torus)
Audio-visual classification on edge and neuromorphic platforms requires high recognition accuracy under tight power constraints. Existing attention-based spiking Transformers still suffer from quadratic attention complexity with respect to audio-visual token length, making deployment on resource-constrained systems difficult. This paper proposes Spikceiver, an audio-visual spiking Transformer that targets efficient multimodal fusion with a compact model size. Spikceiver integrates spiking bottleneck fusion using a small set of learnable Spiking Bottleneck Tokens that attend to each modality to produce compact latent representations for fusion, and an efficiency-oriented Spiking Depthwise-Separable Splitting front-end that replaces vanilla convolution for tokenization. On UrbanSound8K-AV and enhanced CIFAR10-AV (CIFAR10-AV(e)), Spikceiver achieves 95.05% and 89.78% top-1 accuracy with 4.84M MACs and 1.271M and 1.273M parameters, resulting in Efficiency-Accuracy Scores (EAS) of 0.963 and 0.895. Compared with the Multimodal Bottleneck Transformer (MBT-4-256), Spikceiver improves accuracy (95.05% compared with 84.01%, and 89.78% compared with 83.46%) while reducing MACs (4.84M compared with 7.26M) and parameters (about 1.27M compared with 6.40M). Compared with the Spiking Multimodal Transformer (SMMT-1-256), Spikceiver reduces MACs by more than eight hundred times with fewer parameters, demonstrating a favorable efficiency-accuracy trade-off for audio-visual spiking inference on resource-constrained platforms.
Nowadays, Fast Fourier Transform (FFT) and inverse FFT (IFFT) serve as foundational computational kernels in modern signal processing, and notably, as a critical building block in Falcon, a prominent post-quantum cryptography (PQC) digital signature scheme. Unfortunately, most existing memory-based FFT accelerators remain constrained by bank conflicts and arbitration overhead, which limit sustained throughput and energy efficiency in edge and SoC deployments. To address these challenges, this paper proposes Conflict-Free and eXponent-scaled FFT/IFFT (CFX), a co-designed architecture that targets high performance with minimal resource footprints. Specifically, CFX incorporates three key innovations: conflict-free logical bank mapping, stage-wise exponent normalization, and schedule-aware twiddle compaction. The CFX architecture has been implemented and verified at the system-on-chip level on the Xilinx ZCU104 FPGA operating at a maximum frequency of 220 MHz. The SoC design utilizes 13,144 LUTs, 14,604 FFs, 6 BRAMs, and 24 DSPs, with a total power consumption of 3.788 W. Real-time comparisons with powerful CPUs demonstrate that CFX achieves up to 81.4 times higher throughput and up to 524 times better energy efficiency (PDP). Furthermore, compared to state-of-the-art FPGA-based accelerators, CFX delivers throughput improvements of up to 20.88 times and area efficiency improvements of up to 41.8 times.
In heterogeneous multi-core NUMA systems, thread-to-core/node mapping simultaneously affects load balancing, NUMA locality, and synchronization waiting; therefore, no single mapping strategy is optimal for all applications. This paper proposes a heuristic key-metric-driven random-forest mapping selector (HML-RF): with a lightweight Scatter profiling run on a target application to extract a small set of features, HML-RF predicts an energy–delay product (EDP)-optimal strategy among five mapping strategies (Packed/Scatter/HPO/MPO/SPO); in particular, the Synchronization-aware Priority Option (SPO) constructs synchronization priorities using workload and wait-intensity features from profiling data to reduce waiting times. We evaluate on 10 PARSEC benchmark applications (large) in the Sniper simulator, and the results show that HML-RF achieves an average EDP regret of 0.299%, a geometric-mean EDP/Oracle of 1.0030, and significantly outperforms POSM and the best single mapping strategy in statistical tests.
