This study explores the versatility of 1T-nC ferroelectric RAM (FeRAM) memory capable of operating in both secure storage and highly energy-efficient Compute-in-Memory (CiM) modes without incurring any extra design overhead. In contrast to conventional, volatile 1T-1C Dynamic Random Access Memory (DRAM), having significant energy cost due to the continuous refresh cycles, FeRAM presents a robust non-volatile memory solution, enabling efficient data retention with minimal power consumption. Bitwise logic operations (AND, OR) are efficiently implemented using a single, unmodified 1T-nC FeRAM cell and single-row activation (SRA), while NOT operation is realized by a modified sense amplifier. These facilitate bulk bitwise operations with significant energy benefits compared to multi-row based DRAM solutions. Furthermore, we demonstrate key-based (K) cryptographic operations which help in storing Plain Text (PT) in Cipher Text (CT) format tightly coupled with the memory write/read cycles in secure-mode operation with minimal overload while maintaining robust security. In addition, the advantages of vertical 3D integration of 1T-nC FeRAM are evaluated, and thermal profiling of the remnant polarization (PR) is done. Furthermore, we demonstrate that 1T-nC FeRAM memory reduces energy consumption by 31% compared to DRAM by assessing 8 real-world data-intensive workloads utilizing bulk bitwise operations.
Non-volatile in-memory computing (iMC) has emerged as an energy-efficient paradigm well suited to AI work-loads. Its implementation using 1T1C FeMFETs (Ferroelectric Memory Field Effect Transistors), a best-in-class emerging nonvolatile memory technology that integrates BEOL ferroelectric devices with FEOL transistors, is of particular interest. This interest stems from their potential to enable large-scale multiply-accumulate (MAC) operations in both digital and analog domains. However, realizing tangible performance benefits requires comprehensive cross-layer exploration of both design and technology parameters, extending up to accelerator level. In this work, we propose a bitcell-level multi-objective optimization methodology to identify and extract optimal sizing solutions that provide tractable trade-offs between key performance indicators (KPI). We further demonstrate how this approach facilitates cross-stack exploration of accelerator architectures. Results are presented as Pareto fronts spanning 2-4 KPIs: a 2-KPI problem illustrates the methodology, while a 4-KPI problem represents a realistic design scenario. Comparison is made between 130nm and 28nm technologies demonstrating a decrease in the average of write energy and area up to 24X and 30X respectively.
Routing-dominated multi-path architectures play a critical role in enhancing data throughput and resource efficiency in computing, communication, and RF systems. Hence, ensuring matched point-to-point signal arrival is critical to minimizing distortion, latency, and data corruption while managing increased routing density and interconnect complexity. In this paper, delay mismatch in routing-dominated systems is investigated while assuming negligible mismatch within circuit blocks. A variance-based framework is proposed to quantify and optimize the delay mismatch components across multiple levels of abstraction: the system, block, and layout. To validate this model, systematic routing optimization techniques are applied to an impulse-radio ultra-wideband (IR-UWB) edge-combiner transmitter front end (TFE) operating at 6.5-8.0 GHz center frequency. The TFE requires precise pulse widths in the picosecond range, making it highly susceptible to interconnect-induced delay variability. After optimization, the total variance of propagation delay was decreased by 94.37% based on post-layout simulations.
This work presents a time register designed for time-domain signal processing, employing a delay line in a ring configuration topology combined with a digital counter to achieve a high dynamic range. The proposed architecture supports both addition and subtraction operations, offering a practical framework for understanding the implementation of such functionalities in the time domain. The register is capable of efficiently processing signals with durations ranging from picoseconds to milliseconds and demonstrating feasibility for physical implementation.
This work presents the evolution of a Three-Level Flying Capacitor Converter (3L-FCC) ASIC design from earlystage modeling and simulation towards full integration in a mixed-signal ASIC. As an intermediate step, the power converter core was first implemented in an analog ASIC, complemented by a System-on-Chip (SoC) integrating an embedded CPU for the digital control loop and FPGA fabric for the modulation scheme. This hybrid platform enabled functional validation and post-silicon testing of the analog stage before migrating the remaining digital control and phase-shifted pulse-width modulation (PS PWM) logic into the ASIC. In the current stage of the project, the control architecture is being migrated to a hardware description language (HDL) implementation, with the goal of enabling full integration into a standard digital design flow for mixed-signal ASICs. An FPGA-based prototype is being used to verify functionality and assess timing performance prior to full integration, providing a validation path towards future monolithic implementation.
