Benchmarking noisy quantum computers for variational workloads requires more than a single best energy number: two backends may reach similar energies while differing sharply in convergence speed, stability, and parameter sensitivity. We present a compact uncertainty quantification driven benchmarking study for the Variational Quantum Eigensolver (VQE), combining Bayesian optimization with Metropolis-Hastings refinement to search a backend conditioned VQE landscape and characterizing each backend by its best observed energy, evaluations to target, objective dispersion, and Sobol sensitivity fingerprint. On a 92 parameters LiH VQE across seven IBM fake backends, Brisbane wins overall (best energy 1.0207, top normalized quality), Kyoto matches its energy but converges five times more slowly, and Osaka trades a modest energy penalty for near optimal speed and low dispersion. The Sobol fingerprints further show that the dominant VQE parameters differ across backends, indicating backend specific robust regions rather than a universal calibration. Uncertainty quantification therefore provides a practical application level view of backend quality for near term variational workloads.
This educational paper presents a modular workshop framework for teaching quantum programming and hardware-oriented reasoning within microelectronics education. The framework integrates five connected instructional elements. They are Qiskit foundations laboratory on gates, measurement, and Bell-state entanglement; a noiseaware quantum arithmetic module featuring GHZ circuits, ripple-carry addition, and quantum carry-lookahead addition; a structured adder-analysis exercise focused on depth, ancilla, and reversible cleanup; a capstone project on noise-resilient and security-aware 4-bit quantum adders; and a bridge from classical machine learning workflows to quantum machine learning. The paper redefines these activities explicitly as learning modules with student learning outcomes, module learning outcomes, assessment options, and discussion prompts. The resulting sequence helps learners bridge from syntax and circuit building to architecture-level trade-offs, noise interpretation, approximate design, and research-oriented thinking, all of which are well-suited for the quantum workforce.
Modern Systems-on-Chip (SoCs) integrate numerous IP blocks interconnected through on-chip buses such as AXI. Gate-level SoC netlists consist of millions of gates and dense interconnect structures, while containing little to no semantic information. The resulting sea-of-gates representation lacks hierarchy, module boundaries, and meaningful signal names, severely complicating structural recovery. This paper addresses the problem of reconstructing meaningful hierarchy in complex SoC netlists by exploiting bus-protocol semantics. We introduce a novel, protocol-driven divide-and-conquer strategy that leverages AXI initiator-responder communication patterns, channel dependencies, and interface regularities to segment the netlist into functionally coherent modules. Unlike prior approaches based on hardware-agnostic graph clustering, our method embeds bus-level knowledge directly into the segmentation process, enabling more accurate boundary detection and reducing fragmentation. We evaluate our approach on gate-level SoC netlists containing up to 87,000 gates and 5 interconnected AXI components. Experimental results show that our method achieves a mean improvement in clustering accuracy of 68.47% and 300.5% in Normalized Mutual Information (NMI) and Adjusted Rand Index (ARI) respectively compared to state-of-the-art community detection techniques. These results demonstrate that protocol-guided structural recovery is a promising direction for accelerating and improving the reverse engineering of complex SoC designs.
N:M sparsity is an emerging paradigm for structurally sparsifying deep learning models. In N:M sparse models, each contiguous block of M weights contains exactly N non-zero entries. Hence, N:M sparsity facilitates efficient hardware designs. However, N:M sparse models rely on compact metadata to index non-zero weights, they inevitably introduce a novel attack surface for adversarial techniques like Bit-Flip Attacks (BFA). To date, the security implications of such bit flips within sparsity metadata remain largely unexplored. This paper presents METAttack, a novel framework to exploit and quantify the vulnerabilities of bit flips in the metadata of 2:4 sparse models. The new attack features Non-Collision Meta-data Attack (NCMA), a stealthier BFA to the metadata which induces downstream misalignment of activations and non-zero weights during the decoding process. Without altering the weight magnitude, METAttack can still compromise N:M sparse models with a few round of bit flips. We validated METAttack across a diverse set of deep learning models and datasets, positioning it a potential threat to the efficient AI models.
In advanced technology nodes, Current Source Models (CSMs) are widely adopted due to their high accuracy. However, IR-drop-induced supply voltage fluctuations increase the computational burden of CSM-based timing analysis. Existing machine-learning (ML) approaches accelerate CSM evaluation by assuming fixed receiver capacitance along the path, which contradicts the variable-load dependency inherent to CSM formulation. In this work, we propose GoG-Predict, a fast and accurate IR-aware path waveform prediction framework. GoG-Predict employs a Graph-of-Graphs (GoG) Neural Network to model the structured interactions among driver cells, load nets, and receiver cells. In addition, a Feature-wise Linear Modulation (FiLM) mechanism is incorporated to account for the impact of IR drop on output waveform. We evaluate GoG-Predict on open-source designs using a commercial 12nm technology. Experimental results show an average waveform error of 2.03% and a 1426x run-time speedup over HSPICE, while achieving 1.63x higher accuracy compared with state-of-the-art ML-based prediction methods.
