This work investigates receiver linearization in a four-antenna multiple-input multiple-output (MIMO) system operating in the presence of a strong blocker. The received signals are first spatially combined using either maximal ratio combiner (MRC) or zero-forcing combiner (ZFC), followed by a dual-input digital post-distortion (DI-DPoD) stage that compensates for nonlinear distortion generated by low-noise amplifiers (LNAs) driven into compression. The DI-DPoD model is derived from a prior calibration of the receiver's nonlinear behavior and leverages both the desired and blocker components at the combiner output. Measurement-based results show that DI-DPoD reduces distortion-induced error power by approx. 20 dB beyond the combiner output, achieving nearly identical normalized mean squared error (NMSE) performance for both ZFC and MRC-based front ends across varying blocker powers, signal-to-noise ratio (SNR) levels, and angles of arrival. The findings highlight the importance of jointly exploiting spatial selectivity and calibrated nonlinear modeling for robust wideband receiver linearization.
A $\mathbf{2 9 0 - G H z}$ push-push square mixer implemented in $\mathbf{2 8}-\mathbf{n m}$ CMOS for sub-terahertz wireless transmitters is presented. Achieving high output power near 300 GHz in CMOS is challenging because mixers often serve directly as the transmitter output stage without a dedicated power amplifier. In the proposed architecture, the LO signal is applied to the gate while the IF signal is injected at the source, enabling improved isolation and independent optimization of LO switching and IF drive conditions. Simulation results show that this injection scheme provides higher $\mathbf{R F}$ output power than conventional mixers. The mixer is biased at $V_{G}=0.8$ Vand driven with $P_{L O}=$ 10 dBm to maximize output power before compression. With an on-chip LO balun and optimized matching network, the prototype achieves -14.8 dB peak conversion gain and -9.3 dBm output power at 290 GHz. Compared with prior CMOS mixers near 300 GHz, the proposed design achieves competitive output power.
This paper presents a power amplifier (PA) for cellular handsets operating in the frequency range 3 (FR3) band that employs distortion compensation. The compensation circuit uses a vector-sum phase shifter in which the phase is controlled by the envelope amplitude, thereby flattening the PA's AM/PM characteristics. The PA was fabricated using a GaAs HBT process. Continuous-wave (CW) measurements at 8 GHz achieved flat AM/PM behavior and peak gain and power-added efficiency (PAE) of 32 dB and 42%, respectively. Measurements with modulated signals yielded an adjacent-channel leakage ratio (ACLR) of -37.4 dBc and an error vector magnitude (EVM) of –34.5 dB, representing improvements of 7 dB relative to operation without distortion compensation.
Line modes emerging at the edge of 2D Chern photonic topological insulators (PToIs) exhibit robust unidirectionality and immunity to disorder and perturbations. When identical line modes are placed in close proximity, far-end crosstalk is inherently suppressed because backscattering is topologically forbidden. However, near-end crosstalk (NEXT) becomes a severe problem. The underlying cause for NEXT is the dispersion crossing of the neighboring line modes within the topological bandgap. Here, we demonstrate that dispersion engineering of coupled line modes provides an effective route to suppress NEXT. We introduce a simple fabrication approach for realizing Chern topological lines by employing permanent magnets to bias YIG-based PToIs. The magnets are modeled to ensure the required magnetic bias profile. Both simulations and experiments confirm $\geq 20 ~\text{dB}$ NEXT suppression between two topological line modes separated by only a few unit cells.
This paper presents a wideband phase-invariant variable gain amplifier (VGA) adopting a gain core and matching network (MN) co-design technique. The core-MN codesign methodology expands the design space by incorporating the phase variation of the MNs, which was often overlooked in conventional designs. This approach enhances design flexibility and enables wideband phase compensation. Specifically, by configuring the gain-dependent phase variation (GDPV) of the MNs and the active gain core to exhibit opposite polarities, the overall GDPV of the VGA is minimized and flattened across a wide frequency range. Implemented in a 28 nm CMOS process, the VGA achieves a peak RMS phase error (RMSPE) of 1.38° and a peak GDPV of 2.78° with a gain tuning range (GTR) of 21 dB within the $\mathbf{S}_{\mathbf{2 1}}$ 3-dB bandwidth $\boldsymbol{(} \mathbf{1 0. 9 - 2 3. 6} \text{GHz} \boldsymbol{)}$.
