Indexing multidimensional data is inherently complex leading to slow query processing. This behavior becomes more pronounced with the increase in database size and/or number of dimensions. In this paper, we address this issue by processing an index structure in parallel. First, we study different ways of partitioning an index structure. We then propose efficient algorithms for processing each query in parallel on the index structure. Using these strategies, we parallelized two multidimensional index structures -- R* and LIB and evaluated the performance gains for the Gazetteer and the Catalog data of the Alexandria Digital Library on the Meiko CS-2.
The dataflow model of computation, in general, and its recent direction to combine dataflow processing with control-flow processing, in particular, provide attractive alternatives to satisfy the computational demands of new applications, without experiencing the shortcomings of the traditional concurrent systems. This should motivate researchers to analyze the applicability of familiar concepts, such as scheduling and load balancing, within this new architectural framework. Effective execution of loop iterations as a means to improve performance and hardware utilization has received a great deal of attention in the past. In this paper we address the problem of scheduling/allocation of DOACROSS loops in a multithreaded dataflow environment. An extension to the staggered scheme-Cyclic staggered scheme-which produces a more balanced distribution of iterations among processors is introduced and its performance improvement in a dataflow and control-flow environment is simulated and analyzed.
The paper considers distributed processing over a switch-based LAN and addresses loss-free routing of non-reserved, bursty data traffic. The approach is based on embedding multiple virtual rings onto the underlying network topology with the following two constraints: (i) each virtual ring is Hamiltonian (i.e., includes each node exactly once), and (ii) rings are mutually edge disjoint. New techniques to obtain such virtual rings in the hypercube and circulant networks are presented. Each virtual ring may operate like a buffer insertion ring with fairness. The routing algorithm on the multiple virtual rings is a generalization of convergence routing and it ensures loss-free and deterministic delivery of bursty traffic. The bounds on the length of routing are studied both analytically and computationally. It is shown that an upper bound of O(N/d) on the maximum length of routing can be obtained on the networks with d virtual ring embeddings
This paper presents on-line perturbation tracking and intrusion removal techniques which are designed to accommodate delays which occur due to monitoring activities. These accommodations eliminate the effect of monitoring intrusion on the execution behavior and the scheduling of the monitored computation. By maintaining an adjusted time view, the intrusion removal system preserves the execution order of processes and the message selection decisions that would have been made in an unmonitored execution.
A new interconnection network composed of 3/spl times/3 switching elements is proposed. This new network is called Palindrome interconnection network (PIN) with hardware complexity identical to its counterparts. Compared with its counterparts, the proposed network is fault-tolerant, as totally disjoint paths exist in the network between any source/destination pair. In addition, for a given routing tag in the PIN, all the other equivalent tags which correspond to the same source/destination pair, can be derived easily. Computing an equivalent routing tag from a given routing tag requires the change of two bits of routing tag, irrespective of the network size, suggesting that rerouting logics can be incorporated into the constituent switching element comfortably without compromising performance. The proposed network exhibits higher terminal reliability than its counterparts.
Global predicate detection is a fundamental problem in distributed systems and finds applications in many domains such as testing and debugging distributed programs. The paper presents an efficient distributed algorithm to detect conjunctive form global predicates in distributed systems. The algorithm detects the first consistent global state that satisfies a given conjunction of local predicates. The algorithm is distributed because the predicate detection efforts as well as the necessary information is equally distributed among the processes.
Low-dimensional k-ary n-cubes have been popular in recent multicomputers. However these networks suffer from high switching delays due to their high message distance. To overcome this problem, Dally (1990) has proposed express k-ary n-cubes with express channels, that allow non-local messages to partially bypass clusters of nodes within a dimension. The paper argues that hypergraph topologies, that provide total bypasses within a dimension, represent potential candidates as future high-performance networks. It presents a comparative study, of a regular hypergraph, referred to as the distributed crossbar switch hypermesh (DCSH), and the express k-ary n-cube, taking into account channel bandwidth constraints which apply in VLSI and multiple-chip technology. The study concludes that the DCSH's total bypass strategy yields superior performance characteristics to the partial bypassing of its express cube counterpart.
We present a mechanism for making a scalable spin lock protocol, the MCS lock, recoverable, thereby ensuring that a lock never becomes permanently unavailable, even if one or more processes using the lock die. This is achieved by modifying the original protocol to write additional information to shared memory and introducing a cleanup process which returns locks to a usable state in case of process death(s). Our method does not require kernel or hardware support other than the swap instruction, and maintains performance comparable to the original protocol (one third as fast in the uncontested case). We have proven the correctness of our scheme in the face of the weak memory models provided by modern systems.
A method for mapping arrays into parallel memories to minimize serialization and network conflicts for lock-step systems is presented. Each array is associated an arbitrary number of data access patterns that can be identified following compiler data-dependence analysis. Conditions for conflict-free access of parallel memories and network are derived for arbitrary power-of-2 data patterns and arbitrary multistage networks. The authors propose an efficient heuristic to synthesize combined address transformation (NP complete) which applies to arbitrary linear patterns, arbitrary multistage networks, and an arbitrary number of power-of-2 memories. The method can be implemented as part of the address transformation (Xor and And) or through compiler emulation. The performance of optimized storage schemes is presented for FFT, arbitrary sets of data patterns, non power-of-2 stride access in vector processors, interleaving, and static row-column storages. Their approach is profitable in all the above cases and provides a systematic method for converting array-memory mapping and network aspects of algorithms from one network topology to another.
Designing a good task allocation algorithm faces the challenge of allowing high levels of throughput, so that tasks are executed fast and processor parallelism is exploited, while still guaranteeing a low level of memory contention, so that performance does not suffer because of limitations on processor-to-memory bandwidth. In this paper, we present a comparative study of throughput and contention guarantees provided by load balancing networks, a new class of distributed, asynchronous algorithms for real-time task allocation in shared memory multiprocessors. Load balancing networks generalize balancing networks, to accommodate tasks with varying completion times.
The authors present a general framework for approximation schemes on parallel processor scheduling. They propose /spl epsiv/-approximation algorithms for scheduling on identical, uniform and unrelated machines when the number of processors is fixed. For each of the three problems considered, they perform grouping on job processing times in order to produce a transformed scheduling instance where the number of distinct task types is bounded. They optimally solve the corresponding mixed integer program and prove that the optimal makespans for the initial and the transformed problems can differ at most by a factor of 1+/spl epsiv/ The complexity of all /spl epsiv/-approximation algorithms is O(n), where n is the number of jobs to be scheduled.
This paper considers the design problems of processor specification and task allocation for embedded computer systems. A partitioning-based representation is proposed that allows these problems to be solved concurrently. An algorithm based on this representation is described that utilizes simulated annealing coupled with a heuristic processor specification technique. This algorithm, named SA2, is compared against three baseline algorithms on a combination of real and synthetic test cases with respect to two figures of merit: hardware cost and run-time. The real test cases are based on commercially developed automotive electronic applications and the baseline algorithms represent a mixture of heuristic approaches with varying degrees of sophistication. For all test cases, SA2 is found to generate near optimal solutions, and the relative trade-off between solution quality and run-time exhibited by the algorithms is quantified and analyzed.
Recently, there has been growing interest in simultaneous exploitation of task and data parallelism in scientific applications and in compiler and runtime support of this combined form of parallelism. In this paper we report on the integration of task and data parallelism on an important irregular application from the VLSI computer-aided design field, namely VLSI layout verification. We report on the implementation, and experimental results of our study on a SUN Sparcserver 1000 shared memory multiprocessor, a CM-5 distributed memory multiprocessor
Workflow management systems automate the execution of business processes allowing the concurrent execution of multiple process instances. Existing systems do not provide a mechanism to guarantee correct concurrent execution and, as a result, it is not possible to coordinate and synchronize different process instances. Part of the problem is that conventional techniques are not entirely suitable for workflow environments. In databases, locks are the basic mechanism. In operating systems, this is achieved using semaphores or monitors. Neither of these approaches is appropriate for workflow applications. A method is proposed to enforce correct interleavings and guarantee mutual exclusion, as defined by the user, between concurrent workflow processes. The proposed protocol takes advantage of the semantic constructs associated with workflow management to solve some complex problems such as dealing with inherited restrictions and the coarse granularity of workflow specifications.
In this paper we propose user-controllable I/O operations and explore the effects of them with some synthetic access patterns. The operations allow users to determine a file structure matching the access patterns, control the layout and distribution of data blocks on physical disks, and present various access patterns with a minimum number of I/O operations. The operations do not use a file pointer to access data as in typical file systems, which eliminates the overhead of managing the offset of the file, making it easy to share data and reducing the number of I/O operations.
The main contribution of this work is to show that a number of seemingly unrelated problems in database design, pattern recognition, robotics, and image processing can be solved simply and elegantly by formulating them as instances of a general problem-the multiple query (MQ) problem. An arbitrary instance of the multiple query problem consists of a collection A={a/sub 1/, a/sub 2/, ..., a/sub n/} of items, a collection Q={q/sub 1/, q/sub 2/, ..., q/sub m/} (1/spl les/m/spl les/n) of queries, a decision problem /spl phi/:Q/spl times/A/spl rarr/{"yes", "no"}, and an associative and commutative function f operating on subsets of A. For every query q/sub i/, let S/sub i/ be the set of items a/sub j/ in A for which /spl phi/(q/sub i/, a/sub j/)="yes". The solution of q/sub i/ is defined to be f(S/sub i/). In this context, the multiple query problem involves solving all the queries in Q. We begin by showing that if the collections A and Q are stored one item and at most one query per processor on a mesh with multiple broadcasting of size /spl radic/n/spl times//spl radic/n then any algorithm that solves the MQ problem requires /spl Omega/(m1/3n1/6) time in the worst case. Second, we show that a number of fundamental problems can be solved simply and elegantly by formulating them as instances of the MQ problem.
A sorting device capable of sorting p items in constant time is called a p-sorter. It is known that the task of sorting N items using a p-sorter requires at least /spl Omega/ (N log N/p log p) applications of the p-sorter. This bound is tight: there exist algorithms that use O (N log N/p log p) calls to the p-sorter to sort N items. However, there is no known implementable algorithm that can sort N items in O(N log N/p log p) time using a p-sorter. The main contribution of this paper is to propose a simple VLSI architecture and to show that in our architecture N items can be sorted in O(N log N/p log p) calls to the p-sorter, while enforcing conflict-free memory accesses. An important feature of our design is that the total additional VLSI area for hardware, other than the memory for data and the p-sorter, is kept to a minimum.
The authors present a new optimization for or-parallel logic programming (Prolog) systems, called last alternative optimization (LAO). The LAO follows from the flattening principle and the principle of duality of or-parallelism and and-parallelism. Originally LAO was conceived as the dual of last parallel call optimization, an optimization developed for and-parallel systems. LAO enables Prolog programs that have data-or parallelism to execute more efficiently. It also enables more efficient (parallel) execution of constraint logic programs over finite domains. LAO is a fairly general optimization and can be readily applied to virtually any parallel system that exploits nondeterminism (e.g., parallel search based artificial intelligence systems). Last alternative optimization has been implemented in the ACE parallel Prolog system. The performance results indeed prove the effectiveness of LAO. They present a second optimization based on the flattening principle, called balanced nesting optimization (BNO), that is related to LAO, and that also leads to reduction of parallel overhead.
The authors propose a new class of interconnection networks called recursive hierarchical swapped networks (RHSN) for general-purpose parallel processing. The node degrees of RHSNs can vary from a small number to as large as required, depending on recursive and hierarchical composition parameters and the nucleus graph chosen. The diameter of an RHSN can be asymptotically optimal within a small constant factor. They present efficient routing, semigroup computation, ascend/descend, matrix-matrix multiplication, and emulation algorithms, thus proving the versatility of RHSNs. In particular on suitably constructed RHSNs, matrix multiplication can be performed faster than the DNS algorithm on a hypercube. Furthermore, ascend/descend algorithms, semigroup computation, and parallel prefix computation can be done using algorithms with asymptotically fewer communication steps than on a hypercube.
B-trees are used for accessing large database files, stored in lexicographic order on the secondary storage devices. Algorithms for concurrent B-tree data structures achieve only limited speedup when implemented on a parallel computer. To improve the performance, we propose a variant of the B/sup link/-tree, called the B/sup mad/-tree, which allows insertion without node splits, with multiple access in its leaf nodes, and dilation in both the index and the leaf nodes. Parallel algorithms for search, insert and restructuring are designed for partitioned, locked and distributed models. Only part of an insertion node is locked during the insert, and simultaneous insertions by multiple processors in the same node are allowed. A restructuring algorithm runs periodically in the background and requires at most one wait by any search or update operation. Our implementations demonstrate that the B/sup mad/-tree algorithms outperform the best known B/sup link/-trees, and compare favorably with linear hashing. We achieve good speedup (e.g., 4.79 with 8 processors) for partitioned algorithms, and moderate speedup (2.49 with 8 processors) for locked algorithms, even including overhead costs. The insert times obtained for B/sup mad/-trees are 50% to 60% less than that for the B/sup link/-trees in partitioned implementations, and 70% to 80% less in locked implementations. The speedup results on the distributed memory platform (a network of workstations) were not that encouraging due to high communication costs.
