Purpose This paper aims to present a robust wide-input low-dropout regulator (LDO) for automotive and industrial power-management applications. The proposed LDO operates across a wide input voltage range from 7 to 40 V, delivering a regulated 5 V output for low-current analog and mixed-signal subsystems. The main design objectives are to improve high-voltage tolerance, startup reliability and reference stability under harsh supply and temperature conditions. Design/methodology/approach The proposed architecture combines a hybrid high-voltage/low-voltage (HV/LV) MOS isolation strategy with a digitally supervised startup and reference-handover mechanism. High-voltage MOS devices are selectively used at input-stressed nodes to isolate excessive voltage stress, while most analog control and reference circuits are implemented with low-voltage devices to improve transconductance and design efficiency. During startup, a constant-gm bias circuit provides a temporary reference to initiate regulation. Once the output voltage reaches a stable operating level, a comparator and a 4-bit digital counter control the handover from the constant-gm reference to the bandgap reference. An on-chip 550 kHz clock generator is integrated to support the digital counter without requiring external timing signals. Findings The proposed LDO was implemented using a 0.25-µm 1P3M CMOS process and verified through circuit-level SPICE simulations. The regulator achieves stable operation across a 7 to 40 V input-voltage range, delivers a regulated 5 V output and supports a maximum load current of 25 µA. The bandgap reference provides an approximately 1.2 V reference voltage for steady-state operation. Full process−voltage−temperature simulations were performed across TT, SS, FF, SF and FS process corners, an input-voltage range of 7 to 40 V and a temperature range from −40°C to 125°C. In addition, 200-run Monte Carlo simulations were conducted to evaluate the effects of device mismatch on reference voltage, output voltage and startup transition timing. The results confirm stable regulation, deterministic startup behavior and successful prevention of zero-current equilibrium under slow input-ramp conditions. Key simulated performance metrics: They include a dropout voltage of 1.0 V at a 25 µA load, line regulation of ±0.2% over the 7–40 V input range, load regulation of ±0.5% across the 0–25 µA load range and a temperature coefficient of 200 ppm/°C from −40°C to 125°C. Originality/value The main contribution of this work is not limited to extending the input-voltage range of an LDO, but lies in the system-level integration of high-voltage isolation, low-voltage control circuitry and digitally supervised reference handover. Compared with conventional wide-input LDO designs that mainly emphasize regulation accuracy or transient response, the proposed design explicitly addresses startup determinism and high-voltage domain isolation in a self-powered architecture. The hybrid HV/LV MOS strategy improves practical implementation efficiency, while the digitally supervised startup mechanism ensures reliable activation before the bandgap reference takes over. These features make the proposed LDO suitable for low-current automotive and industrial power-management systems requiring wide-input tolerance, stable startup and robust operation under process, voltage and temperature variations.
Purpose With the rapid development of smart grids and renewable energy, higher requirements are placed on the accuracy and efficiency of power metering. To address the limited accuracy of traditional analog-to-digital converter sampling schemes and the large size and high cost of discrete-component time-division multipliers (TDM), this study aims to design a high-precision, low-power power metering integrated circuit based on a TDM architecture, which achieves monolithic integration while maintaining superior metering performance. Design/methodology/approach Using frequency domain modeling, the core modules of the system are abstracted into an oversampling modulator and a multiplier. The sources of error, such as phase shift, nonlinearity and quantization noise, are accurately analyzed. A phase-shift-free pulse width modulator structure and a notch filter optimized using the root locus method are proposed to compensate for phase errors and suppress harmonic interference. Findings Simulation results show that under typical process angles and room temperature conditions, the chip metering error is 21.25 ppm and the error does not exceed 33.07 ppm across all process angles and within a temperature range of −40°C to 85°C. Under 10% total harmonic distortion conditions, the suppression errors for the third and fifth harmonics are better than 45 and 52 ppm, respectively. The total system power consumption is 11.8 mW, with the analog core power consumption being less than 9.8 mW. This integrated circuit outperforms traditional digital solutions in terms of accuracy, integration and power consumption, providing an effective monolithic integrated solution for high-precision power metering in smart grids. Originality/value This study presents an original monolithic integrated solution for high-precision power metering by combining a TDM architecture with advanced error compensation techniques. The proposed phase-shift-free pulse width modulation structure and root-locus-optimized notch filter effectively improve measurement accuracy and harmonic suppression while maintaining low power consumption. Compared with conventional digital-based metering solutions, the developed chip achieves superior integration, accuracy and energy efficiency, providing a practical and scalable approach for next-generation smart grid power measurement systems.
Purpose This study aims to investigate the multiphysics dynamic response of a resonant beam with an insulating substrate under electron irradiation. The focus is on revealing the electromechanical coupling effects between charge accumulation, structural deformation and the device’s micromechanical properties induced by electron beam irradiation, addressing critical reliability gaps in aerospace applications. Design/methodology/approach This paper establishes a Geant4-COMSOL coupling framework to simulate the response of silicon-based microelectromechanical system (MEMS) accelerometer structures under electron beam irradiation of 10–50 keV. Geant4 calculates spatial energy deposition, which COMSOL uses for multiphysics analysis. The authors evaluated varying beam energies (10–50 keV) and substrate materials, validating their predictive models with in situ scanning electron microscopy (SEM). Findings Ionization-induced charge accumulation and transient discharge within the SiO2 substrate drive the resonant beam’s nonlinear periodic oscillations. With increasing energy, structural displacement exhibits a nonmonotonic “decrease–increase–decrease” trend, while oscillation periods shorten. Comparisons with Si substrates confirm the SiO2 insulator’s decisive role in this response. Originality/value Combining in situSEM with cosimulation, this paper unveils the charge-induced discharge mechanisms causing nonlinear MEMS oscillations. These insights offer a crucial theoretical foundation for developing highly reliable, radiation-hardened microsystems for extreme space environments.
Purpose This study aims to realize large-scale and high-density manufacturing of conformal electronic devices by proposing a polydimethylsiloxane (PDMS)-based flexible packaging method via a 12-inch wafer-level redistribution-layer-first (RDL-first) process. Design/methodology/approach PDMS is used as the substrate to fabricate a conformal prototype, owing to its excellent processability, high flexibility and low cost. Electrical simulations show the series resistance and inductance of the daisy-chain structure. Mechanical simulations predict the stress distribution of the packaged structure under a 73.9 mm curvature radius, verifying its mechanical safety when embedded in a cranial mold. Experiments elaborate the process flow, mainly including temporary carrier preparation, RDL layer fabrication, chip flip-bonding and PDMS molding, successfully demonstrating a primary intelligent cranial prototype for signal processing and transceiving. Findings Mechanical simulations reveal that the maximum stress in the prototype when conformal to the cranial mold is 894.16?MPa with a PDMS thickness of 0.16 cm. The simulations also find that increasing PDMS thickness and reducing silicon thickness effectively lowers the maximum von Mises stress. A radio frequency (RF) signal processing prototype is precisely fabricated, containing four dies packaged in a dimension of 30 × 31.5 × 1.6 mm. It shows good flexibility with a minimum bending radius of 43.50 mm. The electrical test results demonstrate high consistency with the simulation results. Originality/value This work provides a processable, low-cost and high-efficiency packaging strategy for conformal electronics. PDMS encapsulation and 12-inch RDL-first wafer-level packaging process are combined. It may provide new strategies to wafer-level packaging technology in flexible applications.
