FPGAs are increasingly incorporated in many high-end robotics applications, often involving computer vision and motor control. However, functional verification of FPGA designs is labor-intensive, time-consuming, and consequently expensive. Moreover, validation of complex systems, such as robots, poses even further challenges because neither the external interactions can be easily modeled with traditional testbenches nor the robot’s response can be adequately observed and ascertained. This work presents a new methodology that validates the robot’s behavior in a realistic simulated environment before transferring the design to the physical robot and the onboard FPGA. This methodology allows integral, fast, and flexible debugging cycles of robotics applications by integrating the functional simulation of the processing unit (FPGA) with the simulation of the robot, its environment, and their mutual interconnections. The Verilator simulation tool is used for fast Verilog/SystemVerilog verification and simulation. ROS, the standard robotics middleware, and Gazebo 3D robotics simulator are used for realistic robot simulation, including a robust physics engine. We have implemented several open-source software extensions to interconnect the Verilog circuit with the simulated ROS sensors and actuators. This methodology’s utility and correctness have been assessed by developing a complete proof-of-concept FPGA-based robotics application in which a commercial robot follows a colored object using its onboard camera and differential drive motors. This work establishes the foundations for developing and testing complex robot FPGA-based modules more efficiently and flexibly.
In time-critical & safety-critical image classification applications, Convolutional Neural Networks (CNNs) based Inference Engines (IEs) are preferred and required to be fast, accurate, and cost-effective to meet the market demands. The self-feature extraction capabilities use millions of parameters and neurons in the stack of layers with restricted processing time. This paper reviews strategies applied in Hardware-based image classification CNN inference engines. The acceleration strategies are (1) Arithmetic Logic Unit (ALU)-based, (2) Data flow-based, and (3) Sparsity-based are considered here. Considering benchmark accuracy, the 16-bit mixed fixed/floating point could provide 99 % and 3.75 times more performance than Half-precision floating point in an application-specific CNN model. Feeding 2-dimensional or 3-dimensional data frames to the CNN layers would reuse the data. It optimizes the volume of memory usage and improves the efficiency of the processor array. The pruning of zero/near-zero valued Input Feature Maps (IFMs) and weights leads to sparsity in the data fed to the different layers. Therefore, data compression strategies and skipping the trivial computation (zero skipping approach) would reduce the complexity of the controller. There is a benchmark performance improvement of 1.17 times and 6.2 times in power efficiency compared to dense architecture. Minimizing the complexity of indexing and load balancing controller would improve the performance further.
Lock-in amplifiers are instruments widely used in physics and engineering laboratories, whose invention goes back to the 1940s. Due to the late electronic developments, the former analog implementations have been replaced with digital versions, mainly based on FPGAs (field-programmable gate arrays). The present work, exploiting the last advances in the microcontrollers field, consists in the development of a functional prototype of a low-cost lock-in amplifier based on a microcontroller with similar specifications to mid-range commercial amplifiers. The performance of the prototype has been tested and compared with commercial devices, showing a similar performance in common use cases at a much reduced cost.
In modern computing architectures, sensitive data (red data) is carried out in the same processing units as encrypted data (black data). Due to leaks (internal mixing, coupling ... ), this red data can be emitted in a legitimate radio transmission through a so-called telecom side-channel. This new type of side-channel creates an important threat as it can be passively and remotely processed by a dedicated interception system. This threat becomes even more concerning within the context of the Internet of Things, as the use of low-cost components leads to increased leaks. This paper addresses telecom side-channels on frequency-hopping signals, that are harsh to eavesdrop due to their sporadic nature in both time and frequency domains. To that goal, a wideband interception system is proposed, able to intercept frequency-hopping signals in real time and to extract sensitive red data from it. The system relies on software-defined radios and leverages both hardware and software resources to process a 200 MHz bandwidth in real time. The proposed architecture is capable of detecting jumps on the order of 20 mu s and can therefore track 50,000 jumps per second across 1,024 channels. Finally, the criticality of telecom side-channels in Bluetooth communications is demonstrated through real interception on several microcontroller chips.
With the increasing use of satellites, rovers, and other space exploration devices, Artificial Intelligence (AI) is also becoming an important tool for space exploration, allowing autonomous decision-making and operations in harsh environments. Asa result, there is an increasing demand for reliable and energy-efficient processing platforms in the space industry. Among all processing architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) are becoming popular, particularly in data-intensive applications like machine learning, demonstrating a substantial improvement in the energy efficiency of inference operations while preserving a good degree of versatility. In high-level class space missions, the hardware platforms incorporate radiation-hardened Field Programmable Gate Arrays (FPGAs) and microcontrollers, which do not meet the performance requirements for the aforementioned AI applications. The use of CGRA architectures in space missions is still not widely studied. The main contribution of this work is a comprehensive Design Space Exploration (DSE) activity with our highly parameterized CGRA architecture, exploring the costs associated with various design parameters when targeting AI in the space domain. We evaluated performance, power consumption, and area occupation after synthesis on the radiation-hardened DARE65T standard cell library developed by imec, based on a commercial 65 nm technology process. We characterize different CGRA configurations, comparing them with state-of-the-art solutions used for the acceleration of the AI algorithms. This work highlights Performance, Power, and Area (PPA) results that range from 100 MHz (up to 600 MOps), 2.43 x 104 mu m2 cell area occupation and 0.699 mW power consumption, to 625 MHz (up to 3.75 GOps), 2.43x105 mu m2, 46.5 mW . During DSE activity, we highlight the optimal solutions in terms of area efficiency (up to 313.1 GOps/mm2) and energy efficiency (up to 289 GOps/W) of each CGRA configuration.
