Through Mold Via Technology for Multi-Sensor Stacking

With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8” to 12” in diameter, while future developments will deal with panel sizes up to 470 × 370 mm 2 . The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lamination and were metalized together with the vias for chip interconnection. Reliability of the manufactured through mold vias with different via diameters and pitches was evaluated by moisture sensitivity level [MSL] testing, temperature cycling and humidity storage and test vehicles were analyzed both non-destructively and destructively. Results show high reliability potential of the introduced through mold via technology as samples have passed MSL 1 and more than 3000 temperature cycles and 3000 hour humidity storage without any electrical failure. The embedding and stacking technology is demonstrated for a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by the through mold vias and soldered to a base substrate. Concluding, within this paper on mold embedded SiPs both is shown - the development of TMVs, an advanced and low cost 3D packaging feature and demonstration of use of this feature for the assembly of a functional 3D multi-sensor system, illustrating the miniaturization potential of 3D system integration.