The thermal concept of the electronic package for high power devices needs to address the increased temperature of operation and the need to insure the head dissipation of the device. In common Fan-out packages Epoxy Mold compounds (EMC) are used which is not well adopted to high temperature operation as EMC has a low thermal conductivity. In this paper the research on the development of a Fan-Out Wafer Level Package is described. First a FEM simulation comparing a Mold compound and SiC Fan-out Packages was performed. It showed that the thermal resistance of the package can be reduced by 72% allowing up to 20 W/mm2 eight times power loss in a 3.9 mm2 package. Later a manufacturing process was developed for this SiC Fan-out Wafer level Package which suits for high power application addressing. For this package Wafer Level bonding techniques of SiC Wafers are used to embed the active chip, e.g. a Monolithic Microwave Integrated Circuit (MMIC). Through SiC Vias (TSiCV) are used to realize the backside contacts and a SiC nanoparticle filled adhesive is used to inprove the thermal conductivity of the bond interface.
This work demonstrates wafer-level thin film encapsulation (TFE) [1], [2] of a radio-frequency microelectromechanical systems (RF MEMS) device with rerouting of contacts and pads for flip-chip compatibility to a much smaller CMOS chip. RF MEMS devices are a key market driver for growth in the MEMS industry. This article enunciates the optimization of lithography steps in defining redistribution layers (RDL) and opening bond pads on high topography RFMEMS wafer to reduce RC delay and match bond pad locations for Heterogeneous integration of MEMS with ASIC.
Silicon Carbide (SiC) based power modules are widely used in the 5G communications, electric vehicle, aerospace, marine, energy and other industrial fields. Different from the consumer electronics application, automotive grade SiC power devices are operation with higher junction temperature, higher power density, higher switching frequency, and harsher environment, the reliability of the power module is particularly important. Power cycling testing is one of the critical tests used for the reliability assessment of the power semiconductor devices and power module development. Power cycling test periodically applies a current to the devices integrated in the power module. This leads to power loss in the entire module and results in a rise in the temperature of the power devices, as well the ununiformed temperature distribution in the power module. In this paper, thermal analysis is conducted for a 6-in-1 double side cooling SiC power module. The temperature distribution of the power module is simulated and the junction temperature of the SiC power devices in the power module is analyzed. The junction temperature difference under different power cycling test conditions is evaluated, and final test condition of the power cycling test for the developed 6-in-1 power module is proposed.
In this study, the low cycle shear fatigue performance and fracture behavior of microscale ball grid array (BGA) structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints with various shear amplitudes were systematically investigated at different current densities by experimental, theoretical methods and finite element analysis. The experimental results showed that the fatigue life of the solder joint decreased with increasing shear amplitude and current density. The descent rate of fatigue life decreased with increasing shear amplitude at the same current density. Moreover, the deterioration of current stressing on the fatigue life of the solder joint was more serious at the lower shear amplitude. In addition, with increasing current density, the solder joint fracture position transitioned from the solder matrix to the solder/IMC layer interface, and the shape of the fracture path shifted from arc-shape to flat-shape.
Board level reliability, such as solder joint reliability under temperature cycling, is essential requirement for electronic packages. At the design stage, many optimization methods are adopted like geometry, structure, and materials. Finite element analysis (FEA) is a powerful and efficient tool to assess reliability performance. However, FEA simulation is still time-consuming for numerous DOE runs. In this study, combining statistical software and FEA analyses, regression equation is generated for quick assessment on solder joint reliability (SJR) by choosing an example of effect of solder joint shape on SJR performance. Interaction of different parameters can be considered in the equation. This provides an efficient and accurate methodology for design optimization and improvement with saving cycle time for new product introduction (NPI). Such methodology can be extended to other areas to make design-for-reliability more robust and efficient.
In this paper, a novel design of centrifugal blower called Plated Blowers (PB) is proposed for cooling of laptop computers where the conventional rotor blade is replaced by a new design comprising of a sheet metal rotor with punched holes and residual hanging chads. A numerical study was conducted on these designs to determine the flow rates under operational speed of 6000 rpm. The results showed that the PB designs can outperform the traditional blade fan design as well as the Volumetric Resistance Blower (VRB) [1] in terms of air flow rate at iso-rpm conditions. Similar to VRB which has a porous rotor, the PBs are also expected to offer significant acoustic advantage over bladed fans (claim to be validated through tests), which can result in a boost in overall platform power in these mobile computing systems.
Development of chip to wafer hybrid bonding (C2W-HB) process is essential to achieve direct bonding of fine pitch (≤ 10 μm) Cu interconnects for heterogeneous integration. As the polymer mechanical behavior is more complex, C2W-HB with direct bonding of Cu/polymer-dielectrics requires significant experimental efforts, resources, and time to design the test vehicles and formulate the process recipe for high quality and yield. In this work, numerical simulations are performed to evaluate the bonding progression for a special case where SiO2 dielectric is used for the bottom wafer and polymer dielectric is used for the top dies. As these two materials are quite different in their thermomechanical behaviour, bonding of the Cu/Cu interfaces depends on the relative expansion/contraction of the surrounding SiO2 (bottom wafer) and dielectric polymer (top die) interface. Our simulations help to elucidate the mechanics at the bonding interface and explain the reasons for the bonding failures observed in the experimental runs. The simulation results show that Cu pad dishing is not suitable for this configuration and protrusion of Cu pads is required to get a successful Cu/Cu direct bonding.
This work describes the details of a fluxless thermal compression bonding process using an in-situ oxide reduction method. Current, TCB processes mainly rely on dip fluxing of the chip or/and pre-applied fluxing of the substrate to achieve removal of oxides. In some instances, an inert environment e.g. N 2 is maintained during the TCB process. A post bonding flux cleanup is generally required, however, there are some near zero residue fluxes that my not require cleaning but these fluxes have the tradeoff that they are not very good at removing oxides. Flux cleanup becomes even more challenging as the chip area and interconnect density is increased. We have developed an in-situ oxide reduction method using localized delivery of formic acid vapors just prior to the bonding step. This method avoids fluxing and post-bonding cleanup steps. The resulting bond quality is equally comparable to the conventional flux based TCB bonds. Furthermore, the FA based oxide reduction is further extendable to the direct Cu-Cu TCB processes
With the advancement of 3D packaging, hybrid bonding is the most widely explored technology for heterogeneous integration and stacking of dies. For the hybrid bonding, prior measurement of the surface roughness, dielectric erosion, and dishing/protrusion of the copper bond pads is critical to check the quality of the fabricated wafers. Generally, atomic force microscopy (AFM) is used to collect the surface morphology of the wafers, and then the manual measurement is done for each scanned file which is quite time-consuming. Therefore, in this article, an automated method of analysis of AFM data was developed in Python to measure critical surface parameters on the wafers used in hybrid bonding. The Python code was used to measure the surface roughness, dishing/protrusion of bond pads with different shapes, i.e., circular and square. The use of the code provides a quick, efficient, first-order analysis methodology for evaluating the quality of the bonding surface, thereby, significantly reducing the manual time required in data crunching.
In this paper, the influence of epoxy molding compound thermomechanical material properties on die top silicon nitride passivation stress during temperature cycling on a high-power surface mount device was studied. The combination of EMC properties (Tg, CTE, and modulus) using different advanced EMCs to achieve lower tensile stress on SiN passivation layer for a high-power SMD was successfully investigated through material characterization, assembly and delamination performance, thermo-mechanical stress simulation, reliability testing, and passivation layer integrity check after TCT. Furthermore, stress relief mechanism related to the mold compound property was proposed based on the results of the study.
During the board level TCT (temperature cycle testing), the dominant failure mode is solder bulk fatigue. However, in some specific cases, track crack was found occasionally in the substrate or PCB (printed circuit board) depending on the assembly capabilities and structural parameter variations. There are several reasons that result in trace damage such as oxidation in copper or micro-voids propagation during thermal treatments, and stress concentration at critical points. This study mainly focuses on the mechanical behavior of structures, so FE (finite element) model is used to analyze the weakness of the detailed geometry on PCB trace and then provides some optimized design options. The targeted traces are built at the location under chip edge. Investigations include choosing the better size of width and thickness, minor shifting the die location in package, and rotating the trace angle properly. Although SJR (solder joint reliability) is one of the indexes for product specification, a good understanding of failure risk will help to prolong the lifetime cycle when there is some room to adjust the board layout.
In this article, EOS-induced failures of three FPGAs due to the severe voltage over or under shoots during debugging process are analyzed, based on well designed procedures. The traditional techniques used are capable to pinpoint and characterize the details of EOS-induced failures, this may assist the manufacturers and users to do the provenance-tracking and improve the reliability of FPGAs application.
Transfer of solder paste for manufacturing of electronic assemblies is a crucial process step for final product quality. While the most common technologies are stencil- and screen-printing, dispensing of solder paste can be seen as an alternative, especially for three-dimensional circuit carriers and small-scale production. Nonetheless, dispensing lacks in process speed and suffers from anomalies in the process, such as insufficient solder paste transfer. In this paper, we investigated a data-driven approach to predict quality of these solder depots in terms of height, area and volume including both process data and previous dispensing quality itself. This work contains three steps. First, a suitable data set was generated by means of Design of Experiment and the dispensing steps based on it. The data was first statistically analyzed. For the model development primarily using automated machine learning (AutoML) is chosen as an approach, in order to reduce model development time and hyperparameter tuning. Furthermore, a deep neural network is trained as a comparison. The performance of the AutoML model ensemble outperforms both the neural network and the statistical benchmark for all quality parameters considered: height, area and volume of the deposited solder paste. The best models offer an R2 score of 0.71 for height, 0.89 for area and 0.81 for solder paste volume, on a separated test dataset. Thus, indicating strong correlation.
Double molding fan-out wafer level packaging process integration flow was introduced in this paper to achieve miniature scale Antenna-in-package AiP at low transition loss with long distance communication and beam steering capabilities. The size of this package as 12mm × 12mm × 0.40mm. The main components of this package are three redistribution layers (RDL), two mold-compound layers and a through mold via (TMV) structure at 100um depth. A bare silicon chip at 4mm × 4mm was embedded into mold compound layers, with copper metal and polyimide dielectric RDL layers built to interconnect the PCB and the opposite metal ground via Metal TMV structure. Copper antenna was fabricated on top of thick, second-molded-compound layer via IME technology on double molding FOWLP process architectures. This paper demonstrated a double molding fan-out approach to build RDL layers on first-mold reconfigured silicon surfaces; and second mold as the objectives of filling up TMV structures and dielectric interlayer between RF metal and antenna metal layers. The major process challenges and the respective solutions were discussed. The development of critical process parameters was identified to ensure good process specifications and uniformity.
Hybrid bonding with 3D stacking of thin chips for high bandwidth memory is a widely explored packaging technology. In this study, thin memory wafer fabrication is demonstrated for multichip stacking applications of up to four chips using the hybrid bonding technology. For the first time, damascene fabrication processes have been established and optimized for 50 µm thickness temporary bonded wafers. The test vehicle was designed with a chip size of 13 × 6 mm and a substrate size of 15 × 8 mm. The minimum trace width and spacing in the routing layers is 2/2 µm. The hybrid bonding pad is designed with 5 µm and 3 µm in diameter while the pitches are maintained at 10 µm and 6 µm respectively. Test chips and substrates are designed for back-to-face bonding, and for chip backside, both inorganic and organic dielectric materials are evaluated. Memory chip stacking was evaluated using dielectric materials to identify the assembly process window establishment and mechanical integrity of the stacking.
This paper demonstrates the 3D heterogenous integration of integrated circuit chips through a vertical stack-up (of SiPs) approach to achieve significant reduction in form factor with improved performance. In this paper, the process integration of high aspect ratio via-last TSV in a LNA SOI wafer will be described. The final aim of this work is to allow a 3D integration for RF front ends as schematically shown in Fig. 1. The front side metallization on the LNA device wafer includes one layer of Cu BEOL while the backside of the wafer consists of one Cu re-distribution layer (RDL) interconnect layer. The RF testing will be performed to verify the TSV and interconnections on LNA SOI wafer. Fig. 1 shows the schematic of test vehicle with filter chip assembled on LNA wafer with TSV for demonstration purpose.
With facing the limit of Moore's law, semiconductor packaging is getting more important. TSV is attracting for next generation packaging technology with advantages such as shorter interconnection length, less transmission delay and faster communication speed. However, as the packaging scale is reduced, it is becoming important to control the performance degradation due to parasitic elements in the TSV array structure. In this paper, parasitic capacitance was simulated using commercial FEA tool based on design of experiment. As a result, it was found that among the three factors, size, aspect ratio, and pitch had the greatest influence in the order. Also, size interacted with other factors, yet there was no significant interaction between pitch and aspect ratio.
In this paper, the analysis of the board level reliability of a Radar package continuously studied in parallel to its progressing design development will be presented. In general, the studied Radar package follows the concept of an interposer-like antenna board, carrying the Radar antenna patch but also connecting the Radar device to the PCB in BGA manner. The signal processor and antenna driver ICs are packaged in a fan-out wafer level package that is assembled to the antenna board as a BGA land side package. The board level reliability of the Radar device was investigated considering variations of the package design and package and interconnect materials. Test conditions were selected in conformance to the AEC-Q100 standard for board level reliability testing. Intermediate electrical read-outs were executed to monitor the sample health including the check of single I/Os at different I/O locations with regard to the BGA grid. As of now, all antenna board configurations were tested for at least 1,000 temperature shock test cycles. Selected configurations reached 3,000 cycles. In these tests, Radar demonstrator samples achieved a characteristic TCoB life of more than 2,000 cycles. Solder fatigue behaviour was found to be the root failure cause.
Pressure copper (Cu) sintering paste with high shear strength, high thermal/electrical conductivity, and positive reliability was developed for high-power device die-attach applications. The paste is suitable for different metallizations, e.g., Au, Ag, and Cu. When sintering with 15-20MPa pressure, > 60MPa shear strength was achieved for 3mm x 3mm joints and> 30MPa for 5mm x 5mm joints. After more than 1000 hours (250°C) aging and 3500 cycles TCT (−40°C-17 SOC), the joints exhibited excellent performance without delamination. Shear strength increased with increased TCT cycles. This Cu sintering paste can be used for both dispensing and printing applications. For strong bonding between die and substrate, the sintering process requires N2, H2, formic acid, and a vacuum atmosphere.
In the semiconductor industry, defect detection is very important as it affects performance. In Hybrid Bonding, identifying defect types prior to bonding is critical in determining bonding performance. To overcome this challenge, we propose a solution involving Computer Vision and Deep Learning to accomplish classification of these defects with limited availability of data. With this approach, the defect identification time is reduced, thereby driving faster research and product development.
