Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A redistribution layer is applied on the reconfigured wafer and routes the die pads to the space around and on the die. After bump formation and package singulation by dicing an SMD compatible package is completed. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold vias or vertical interconnect elements [VIE] and a redistribution layer on both sides of the FOWLP. A Foldable Fan-out Wafer Level Package (FFOWLP) would now allow a single sided planar processing and yield a stacked three dimensional package by folding only. Folding can be implemented by a combination of a flexible redistribution layer and a dicing process that only cuts through the molding compound but leaves the redistribution layer untouched. As foldable redistribution layer e.g. polyimide can be used, a standard for flexible substrates. The feasibility of the proposed technology is demonstrated using a multi-chip package. Dies are mold embedded in wafer size. Subsequently the wiring is done by lamination of a polyimide film over the embedded components. In a process flow similar to conventional PCB manufacturing µvias are drilled to the die pads using a UV laser and metalized by Cu-electroplating. Conductor lines and pads are formed by Cu etching. A solder mask can be applied for pad definition. Finally, the wafer will be diced in two steps. First the bending cuts will be done by dicing only through the molding compound and in a second step package singulation will be carried out. Besides folding for package stacking the technology can be also be used to integrate multi-die packages into free form factor surfaces as bows, curves or defined angles. Upscaling of the technology described above from wafer to panel is also possible and offers low cost solutions and large/long foldable FOWLP stripes in a well-defined package.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics for heterogeneous system integration. This paper describes the technological path from wafer level embedding to 24"×18" fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as autonomous sensor nodes, packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12″/300 mm diameter. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 24″x18″ or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As a process alternative also lamination as used e.g. in PCB manufacturing can be taken into account.

Today, there is no non-destructive, simple, inexpensive and yet accurate in-situ monitoring technique for cracks and delamination available for routine use in electronic package testing. However, such a method is highly desirable, as delamination testing is part of every qualification programme in industry. Rapid failure analytical techniques which allow introspect and easy-to-interpret information on adhesion loss during stress testing, analogous to e.g. resistance testing for solder joint reliability, would enable considerable speed up of the development process of advanced packaging technologies, especially also for situations where not even classical ex-situ methods like scanning acoustic microscopy or pulse phase thermography are applicable. So this paper proposes a radically new approach using local thermal impedance variations caused by cracks to generate electrically detectable signals by the 3ω-Method, designed as highly local thermal sensors array in analogy to a pixel matrix for readout as image from a delamination camera. We show the proof of concept of the method on an industry-grade flip-chip package, its robustness with respect to electrical readout and the very good correlation between experiment and simulation, enabling unequivocal detection of thermal impedance changes and its insensitivity to cross effects, e.g. moisture ingress. Guidelines and estimations for future applications are given.

For WLP (Wafer Level Packaging) thin film polymers play a key role in respect to board level reliability. This paper introduces a reliability indicator giving a tendency of the polymer material to crack initiation around the UBM pad. This indicator derived from Finite Element simulated maximum stress in polymer layer and the material specific tensile strength. Comparing the simulation results with the experimental data we see the same impact of the mechanical material properties on the reliability. This proves the described reliability indicator as suitable for estimating thermal cycle reliability of RDL polymer materials gives application engineers and manufacturers a new tool for selecting the most suitable RDL material for e.g. flip chip and WLP applications.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12 ''/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18 '' x24 '' or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As an alternative process, lamination can be also considered.Already today PCB technologies offer the potential for large area panel packaging up to 24 '' x18 ''/610 x 457 mm(2) and can be applied to form a redistribution layer [RDL] for large area reconfigured wafers or panels, replacing thin film redistribution. For PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using LDI techniques for maskless patterning. State of the art equipment and materials the manufacturing of structures down to 20 mu m lines and spaces with a clear development trend to 10 mu m lines and spaces and hence getting close to photolithography thin film structure sizes.Using the above mentioned maskless laser direct imaging technologies (LDI) instead of photolithography have a high potential for further cost reduction with intrinsic process advantages. The LDI cost advantage is backed by LDI availability for large panel sizes, also including 450 mm wafer form factors.Based on the technology described the Fan-out Panel Level Packaging approach will be demonstrated on full 24 '' x18 ''/610 x 457 mm2 format including large area assembly, embedding and redistribution. Related technology challenges as die shift, warpage, panel handling or yield will be discussed in detail. Using maskless LDI technology real die positions could be automatically adapted to the redistribution and hence less accurate die placement can be compensated and higher die shift could be tolerated which is a big advantage when moving towards large area with acceptable yield.In summary this paper describes the technological path from wafer level embedding to 24 '' x18 '' fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as packages for handheld consumer application or biomedical application as sensor integration into microfluidics.

General lighting by use of LED-Chips is one of the strongly growing markets today and also in future. One of the trends goes to LEDs with higher and higher luminous fluxes per chip area to get the best price per lumen on the market. Unfortunately, such large LEDs produce a lot of heat, which must be spread to avoid overheating and shorter lifetime of the LEDs. Another approach is the use of many small LEDs so that both light and heat source are spread into a larger area. Cost-effective established PCB-technology was applied to produce large-area light sources consisting of many small LED chips placed and electrically connected on a PCB-substrate. LEDs were ICA-bonded with their bottom pad to the PCB. The top contacts of the LEDs were established by laminating an adhesive copper sheet followed by a LDI structuring as known from PCB-via-technology. This assembly can then be completed by adding converting and light forming optical elements.

With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8” to 12” in diameter, while future developments will deal with panel sizes up to 470 × 370 mm 2 . The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lamination and were metalized together with the vias for chip interconnection. Reliability of the manufactured through mold vias with different via diameters and pitches was evaluated by moisture sensitivity level [MSL] testing, temperature cycling and humidity storage and test vehicles were analyzed both non-destructively and destructively. Results show high reliability potential of the introduced through mold via technology as samples have passed MSL 1 and more than 3000 temperature cycles and 3000 hour humidity storage without any electrical failure. The embedding and stacking technology is demonstrated for a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by the through mold vias and soldered to a base substrate. Concluding, within this paper on mold embedded SiPs both is shown - the development of TMVs, an advanced and low cost 3D packaging feature and demonstration of use of this feature for the assembly of a functional 3D multi-sensor system, illustrating the miniaturization potential of 3D system integration.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the potential of advanced compression molding processes for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing. PCB based redistribution offers the potential of real large area redistribution up to 610 × 457 mm 2 and the integration of vias (also through mold vias -TMVs) as both are standard features in PCB manufacturing. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding process for the manufacturing of single chip packages, multi chip packages or even heterogeneous systems on wafer scale, typically in 8" to 12" format. The wiring of the embedded components can be done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components and on the wafer backside for double sided redistribution. In a process flow similar to conventional PCB manufacturing μvias and through mold vias are drilled using a UV laser after RCC lamination and are metalized by galvanic Cu process in one step. Conductor lines and pads are formed by Cu etching. Finally, a soldermask and a solderable surface finish are applied - all of them standard PCB processes. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. To evaluate the potential of today's encapsulants for large area embedding processes, different liquid and granular molding compounds have been intensively evaluated on their processability, process & material induced die shift and warpage results. A strong focus was put on the process chain: chip placement on a temporary carrier - compression vacuum molding for embedding - RCC lamination - laser drilling processes for μVias & through holes - metallization structuring - module singulation & 3D assembly. The feasibility of the entire process chain is demonstrated by the fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. A demonstrator with two BGAs with embedded components and PCB based redistribution stacked on each other and mounted on a base substrate enabling the electrical connection of the stacked module was generated. Reliability of the manufactured 3D stacks is evaluated by temperature cycling and is analyzed both non-destructively and destructively. In summary this paper describes the potential of wafer level mold embedding technology in combination with PCB based redistribution processes towards a 3D SiP stack. Technological feasibility of the process flow is proven and a reliability characterization shows the applicability to consumer electronics applications at least. The technology described offers a cost effective packaging solution for e.g. future sensor/ASIC systems or processor/memory stacks providing miniaturization and sourcing advantages known from PoP assembly.

In recent years, within power electronics packaging, there has been a trend toward compact power electronics modules for automotive and industrial applications, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics, yielding maximum miniaturization. Transfer molding is the method of choice for cost-effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package. Typically, these packages are asymmetric, and thus a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed, providing a heat path for optimized cooling. This asymmetric geometry is prone to yielding warped substrates, preventing optimum thermal contact to the heat sink and also putting thermomechanical stress on the encapsulated components, possibly reducing reliability. Such packages are truly heterogeneous, combining power ICs, wire bonds, SMDs, control ICs, substrate, and lead frame surfaces. As a result, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally, those packages need to operate at elevated temperatures for extended time periods, for example, at 150°C for 2000 h and more, so high thermal stability is of prime importance. Within this paper, a reference application is described integrating power and control logic inside a lead frame based molded package. Taking into account the challenges mentioned above, a detailed description of material selection for this module will be given, including material analysis, such as rheology, reactivity, and change in εr; and thermomechanical properties, in initial stage as f(t,T) and after media storage. Process development tools for module molding are used to ensure manufacturability and usability. Concluding rules for encapsulant material selection and package setup are provided.

The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm2. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular moldi- - ng compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area.

As the development of microelectronics is still driving towards further miniaturization new materials, processes and technologies are crucial for the realization of future cost effective microsystems and components. These future systems will not only consist of SMDs and ICs assembled on a substrate, but will potentially integrate also living cells, organelles, nanocrystals, tubules and other tiny things forming a true Heterogeneous System. Futures ICs and passives will also decrease in size, e.g. for RF-ID applications forecast die sizes are smaller than 250 mu m, thicknesses less than 50 mu m and pitches way below 100 pm, passives, if not directly integrated into the system carrier, will be even smaller. New placement and joining technologies are demanded for reliable and low cost assembly of such applications, as today's packaging technologies only allow the assembly of those small dies and components with a very high effort and for this reason with high cost. With ongoing miniaturization also the protection of the microsystems mostly realized by a polymer needs to be decreased in thickness, yet providing maximum protection. Here, besides mechanical stability, humidity barrier functionality is a key factor for system reliability. Fraunhofer IZMs approaches towards packaging technologies facing the demands of future nano-based Hetero System Integration are described within this paper, comprising material and process development. Material developments focus on nano-particle enhanced polymers. One example are materials with optimized humidity barrier functionality, where various filler particles are integrated into a microelectronic grade epoxy resin and investigated regarding their barrier properties. Furthermore, the processing of nano-particle filled polymers is illustrated. Process development comprises touchless handling concepts that are promising for handling miniaturized components, not directly fabricated at the very place where they are needed. Different concepts are under evaluation. Magnetic handling can be regarded as one of the most ripened ones, thanks to the rugged approach explored. Another promising concept is the use of microdroplet manipulation by electrowetting. Results from both concepts show potential for future use. Finally advanced interconnect concepts for low temperature joining by CNT contacts or reactive interconnects are introduced. In summary an overview on nano-based technologies for heterogeneous system integration is given.

Polymer materials - mainly epoxy resins - are widely used in microelectronics packaging. They are established in printed circuit board manufacturing, for adhesives as die attach glues or for encapsulants as molding compounds, glob tops or underfill materials. Low cost and mass production capabilities are the main advantages of these materials. But like all polymers they can not provide a hermetical sealing due to their permeability properties. The susceptibility to water diffusion through the polymer and along the interfaces is a drawback for polymer materials in general. Water inside a microelectronic package might lead to softening of the material and to a decreasing adhesive strength and resulting delaminations close to solder bumps or wire bonds reducing package reliability by decreasing the package structural integrity. During package reflow, the incorporated humidity might lead to popcorning, i.e. abrupt evaporation of humidity during reflow soldering, is one major problem during plastic package assembly. The introduction of high temperature lead-free soldering processes has even increased this issue. Therefore, plastic packaging materials with enhanced humidity resistance would increase package reliability during assembly and lifetime without cost increase and with no changes in processing. The incorporation of nano-particles into plastic packaging materials is discussed as one potential solution for improved humidity resistance as it is a rather low effort approach to material modification opposed to chemical modification of the matrix. To evaluate the potential of such additives concerning moisture resistance the effect of nano-particles mixed with a microelectronic grade epoxy resin is studied. From the large variety of fillers available this work mainly focuses on three different types: nano-sized silica, modified bentonite and zeolites. Working principles of these particles range from large surface impact of nano-particles, barrier functionality due to stacked layer formation and molecular catcher function. Formulations with different particle concentrations and surface modifications are characterized regarding their influence on humidity diffusion, absorption and desorption behavior as well as their influence on other material properties as reaction kinetics, viscosity and thermomechanical properties. Additionally the combination of nanoand standard micro-particles needed for thermo-mechanical adjustment of the polymer properties is studied. Experimental work is accompanied by simulations, in order to provide further qualitative understanding on effects of particle form, size and surface properties. In summary this paper describes the potential of different nano-particles as additives for plastic packaging materials for enhanced humidity resistance/barrier enhancement within microelectronic packages. This topic is gaining increased importance when considering the trend towards System in Package, where a multitude of components is encapsulated to form one SiP that incorporates a large number of different material interfaces and interconnects. All these interfaces and interconnects need to be protected from degradation caused by moisture ingress, without allowing much increased package volume or package cost. Polymers with improved moisture resistance can be one building block of future moisture resistant packages - the results of this study show their large potential for this field of application.

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Transfer molding is the standard process for a highly reliable encapsulation of leaded and area array packages as BGAs or CSPs. Advanced materials and process developments now allow the use of transfer molding technology for direct underfilling and / or overmolding of Flip Chip assemblies. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing or jetting is required. Molded Flip Chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. Trends of the market drive towards SIPs with an integration of different devices. Therefore the highly reliable encapsulation of these hybrid packages with inhomogeneous topography is the goal. For testing the reliability limits and the determination of failure mechanism of molded Flip Chips a test vehicle has been designed at Fraunhofer IZM.

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products such as cellular phones or GPS devices. For both widening Flip Chip technology's application range and for addressing the automotive electronics' volume market, developing assemblies capable of withstanding high temperatures is crucial. A typical scenario for integrating electronics into a car is a control unit within the engine compartment, where ambient temperatures are around 150 degrees C, package junction temperatures may range from 175 degrees C to 200 degrees C and peak temperatures may exceed these values.If Flip Chip technology is used under harsh environment conditions, it is clear that especially the polymeric materials, i.e., underfiller, solder mask or the organic substrate base material, are challenged. Generally, the developmental goal for encapsulants compatible with high-temperature applications are materials with high T, and low degradation even at temperatures > 200 degrees C.According to these demands, a test group of advanced underfill encapsulants has been used for assembling Flip Chip devices. These test vehicles were built using lead-free and lead-containing solders such as SnAgCu and eutectic PbSn and standard FR4 substrates, for evaluating the reliability potential of state-of-the-art underfillers. Material analysis is performed for studying both material degradation as well as temperature-dependent thermo-mechanical and adhesive properties. For assessing reliability, temperature cycling is performed with different maximum test temperatures ranging from 150 degrees C to 175 degrees C. The device status is intermediately analyzed by using electrical measurement for detecting bond integrity and acoustomicroscopy for determining the occurrence and growth of delaminations. Extensive failure analysis is added to investigate device failure mechanisms, especially related to the respective test temperature.In summary, an empirical status of the high-temperature potential of state-of-the-art underfillers and material combinations is attained and an outlook on future demands and developments is provided. (c) 2005 Elsevier Ltd. All rights reserved.

In the field of microelectronics encapsulation transfer molding is the process of choice for high volume and high reliability encapsulation of microelectronics devices. The materials used for transfer molding are highly filled epoxy based systems, with typically good CTE matching to encapsulated components and high media and temperature resistance. Especially harsh environment applications as automotive, industrial or outdoor communication electronics can benefit from the intrinsic advantages of this technology. For the development of such transfer molding processes it is necessary to design and manufacture a precision mold tool, adapt it to the transfer molding system, set up the process parameters and eventually modify the mold tool to yield improved results, e.g. by a variation of the flow fronts. These processes are not only time consuming but also costly, as high precision tooling is needed. To shorten process development times or to allow a larger variation of geometrical variations a rapid tooling process would be helpful. Within the project PowerSmart such a rapid tooling process has been developed using a 3D micro machining system and selected aluminum alloy as tool material. This rapid tooling process was used to manufacture a System in Package that has been developed within PowerSmart. This SiP integrates a Flip Chip and various SMD components; package form factor was a quad flat non leaded [QFN] package, so an area molding process with subsequent singulation by sawing was used. Within the paper the development of a prototyping technology is described and demonstrated with the development of an adapted SiP packaging technology - this is done from concept development and material selection to manufacturing process development.

For improved reliability of microelectronics an encapsulation of sensitive structures is crucial, this is true especially for polymer electronics, where oxygen diffusion and water vapor ingress do dramatically influence the electrical performance. For the protection of semiconducting polymers within organic LEDs a glass layer is the method of choice, providing optimized sealing except for the edge areas. Disadvantage of glass as a sealing material is its rigidity and its sensitivity against mechanical stress. For the realization of low cost applications as smart labels / RF ID tags besides barrier properties also mechanical protection is needed to ensure device functionality. This is especially true when these devices need to operate within harsh environment. Various approaches are possible to apply such barrier layers, typically CVD/PVD or spin coating are used, to yield thin, homogeneous layers of encapsulants of 1 to 5 μm thickness. For the high speed encapsulation of large areas also lamination is discussed, where multilayer films are applied using temperature and pressure, layer thickness is in the range of 5 to 30 μm. As a further technology, suited for the deposition of low viscosity liquid barrier materials, film coating processes are proposed. Focus of the technology development described is the application of homogeneous coating on large areas. Expected advantage is the contactless application at high speed on large area substrates, especially useful on substrates showing a 3D topography, as present with devices integrating heterogeneous structures as organic semiconductors (OSC), printed passives or coils.