Power consumption is a critical design factor in modern mobile chip design, in which the memory system with dynamic random-access memory (DRAM) consumes more than half of the entire system’s power. Without DRAM bandwidth compression, extreme multimedia operations such as 8K high dynamic range (HDR) recording and 8K video conference calling are not possible without sacrificing image quality or trimming because of thermal limitations or battery time sustainability constraints. Since heterogeneous processors are substantially involved in managing various types of fallbacks or software solutions, complicated compression algorithms for high-compression ratios are not actually adaptable owing to timing closure problems or high throughput requirements. In this paper, we propose evaluation metrics to assess lossless embedded compression (LEC) algorithms to reflect realistic design considerations for mobile multimedia scenarios. Furthermore, we introduce an optimized LEC implementation for contemporary multimedia applications in mobile devices based on the proposed metrics. The proposed LEC implementation enhances the compression ratio of LEC algorithms in other commercial application processors for contemporary premium smartphones by up to 9.2% on average, while maintaining the same timing closure condition.

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture, called DAVID II, resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that DAVID II achieves almost linear speedup at best case even in sixteen rasterizers.

72.5GFLOPS GPGPU computing, 240 Mpixel/s sustainable image signal processing and 60fps 1080p multi-format video codec (MFC) capabilities are integrated with an 1.7GHz out-of-order-execution dual-core ARMv7A architecture CPU and 12.8GB/s memory subsystem for a next-generation application processor. The GPU-based general-purpose computing capability can deliver 10× higher energy efficiency in compute-intensive multimedia applications, compared with a CPU solution on the same die. The improved energy efficiency with GPGPU computing enables next-generation fused multimedia applications, with the assistance of dedicated high-performance low-power multimedia accelerators, as well as with low-power design and process technology, as shown in Fig. 9.4.1.

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

In this paper, we introduce a novel write back method named as the adaptive write back method to solve a memory bottleneck problem and to reduce power consumption. The key of this architecture is adaptively changing the timing of write back operation to an external memory. As a result, the proposed architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses. Also we can reduce the peak power which is a critical problem for embedded systems. We have evaluated the new proposed method on 3D graphics pixel cache on a SoC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed method.

In this paper, we introduce 3D graphics cache system to increase memory utilization and solve a memory bottleneck problem for an embedded system. We propose a novel pixel cache and a texture cache for a mobile 3D graphics hardware accelerator. The pixel cache enhances rendering performance by adopting a new write back algorithm and the texture cache also enhances the performance by adopting a multi-level, multi-port and non-blocking architecture. And all caches are optimized for AMBA3.0 AXI on-chip bus protocol Also the proposed cache architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses and improving cache efficiency by implementing novel cache architectures and multiple outstanding transactions. Also we can reduce a peak power which is a critical problem for an embedded system. We have evaluated the new proposed caches on 3D graphics IP on a SOC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed methods.

Current rendering processors are aiming to process triangles as fast as possible and they have the tendency of equipping with multiple rasterizers to be capable of handling a number of triangles in parallel for increasing polygon rendering performance. However, those parallel architectures may have the consistency problem when more than one rasterizer try to access the data at the same address. This paper proposes a consistency-free memory architecture for sort-last parallel rendering processors, in which a consistency-free pixel cache architecture is devised and effectively associated with three different memory systems consisting of a single frame buffer, a memory interface unit, and consistency-test units. Furthermore, the proposed architecture can reduce the latency caused by pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. The experimental results show that the proposed architecture can achieve almost linear speedup upto four rasterizers with a single frame buffer.

This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 um 4-metal process technology.

In this paper, a consistency-free memory architecture for sort-last parallel rendering processors with a single frame buffer is proposed to resolve the consistency problem which may occur when more than one rasterizer try to access the data at the same address. Also, the proposed architecture reduces the latency due to pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. For these goals, a consistency-free pixel cache architecture and three effective memory systems with consistency-test units are presented. The experimental results show that the proposed architecture can achieve almost linear speedup up to four rasterizers with a single frame buffer.

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of an effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture that performs the depth test twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste due to fetching unnecessary obscured texture data by performing the depth test before texture mapping. It also reduces the miss penalties of the pixel cache by using a prefetch scheme-that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. We have built a trace-driven simulator for the proposed architecture. To validate the proposed architecture, the results of various simulations are provided. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption while producing high-performance gains.