本文介绍了电荷俘获的原理以及直流特征分析技术对俘获电荷进行定量分析的局限性,同时介绍了脉冲I-V分析技术,其能够对具有快速瞬态充电效应(FTCE)的高k栅晶体管的本征(无俘获)性能进行特征分析.

The pulsed current-voltage (I-V) measurement technique with pulse times ranging from ~17 ns to ~6 ms was employed to study the effect of fast transient charging on the threshold voltage shift DeltaV t of MOSFETs. The extracted DeltaV t values are found to be strongly dependent on the band bending of the dielectric stack defined by the high-kappa and interfacial layer dielectric constants and thicknesses, as well as applied voltages. Various hafnium-based gate stacks were found to exhibit a similar trap density profile.

Development of High-k Gates for Advances CMOS Devices High dielectric constant (high-k) materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), alumina (Al2O3), and their silicates, have drawn a great deal of attention in recent years for potential use as gate dielectrics in advanced CMOS processes [1]. With high dielectric constants, gate dieletrics can be made thicker than SiO2 while achieving the same capacitance. The result is leakage current that can be lower by as much as several orders of magnitude. However, there are still technical challenges to overcome, such as Vt instability [2-4], carrier channel mobility degradation [5-9], and long-term device reliability [10-13]. One of the important issues preventing implementation of high-k gates is the trapping of charges in the pre-existing traps inside these dielectrics [14-15]. When the transistor is turned on, some of the channel carriers will be accumulated in the gate dielectric due to the vertical electrical field, resulting in a shift of threshold voltage and a reduction in drain current. Fully understanding charge-trapping and these related mechanisms is the key to understanding channel mobility degradation and device reliability problems. However, traditional DC testing techniques may not accurately characterize these mechanisms.

随着器件尺寸的持续减小,以及在器件的制造中不断使用新材料,对晶圆级可靠性测试的要求越来越高.在器件研发过程中这些发展也对可靠性测试和建模也提出了新的要求.为了满足这些挑战需要开发更快、更敏感、更具灵活性的可靠性测试工具.

Since high-k materials are very different from SiO2, both structurally and electrically, conventional characterization and reliability methods that have been developed for SiO2 devices may not be applicable to high-k dielectric devices.Fast transient charging effects degrade the drive current of high-k devices due to electron trapping in the gate dielectric. Because of this phenomenon, conventional DC drain current-gate voltage (I-d-V-g) measurements may underestimate the drain current, which translates to lower extracted mobility values, which has been confirmed by ultra short pulse measurements.The fast spontaneous post-stress relaxation phenomenon could complicate the assessment and interpretation of the threshold voltage (V-TH) instability in high-k devices. The results obtained with a novel inversion pulse measurement method demonstrate that the V-D, relaxes after a post-stress period of a couple of hundred microseconds. Consequently, the magnitude of V-TH instability is underestimated when a relatively slow switching matrix is used for the stress/sense measurements. (c) 2005 Elsevier B.V All rights reserved.

Increasing measurement frequency and using a vector network analyzer permits accurate EOT measurements at thickness less than or equal to0.9nm, aiding the move to smaller device dimensions and thinner gate oxides.

An ultra-short pulse current–voltage ( I – V ) measurement technique has been applied to high-κ gate transistors to investigate the effects of fast transient charging. It is shown that the fast electron trapping may contribute to the degradation of transistor performance (i.e., low mobility) observed with direct current (DC) characterization methods, as well as pulse techniques in the tens of microseconds range and above. In particular, in the samples with significant electron trapping, the drain current in the saturation regime is shown to improve by up to 40% from its DC values when the characterization is performed with pulse I – V measurements in the nanosecond range.

The external quantum efficiency in the spectral wavelength range 5–500 nm of a large active area Pt/n-type GaN Schottky photodiode that exhibits low reverse bias leakage current, is reported. The Schottky photodiodes were fabricated from n−/n+ epitaxial layers grown by low pressure metalorganic vapour phase epitaxy on single crystal c-plane sapphire. The current–voltage (I–V) characteristics of several 0.25 cm2 devices are presented together with the capacitance–voltage (C–V) characteristics of one of these devices. A leakage current as low as 14 pA at 0.5 V reverse bias is reported, for a 0.25 cm2 diode. The ultraviolet quantum efficiency measurements show that the diodes can be used as radiation hard detectors for the 5–365 nm spectral range without the use of visible blocking filters. A peak responsivity of 77.5 mA/W at 320 nm is reported for one of the fabricated devices, corresponding to a spectral detectivity, D*=1.5×1014cmHz1/2W-1. The average detectivity between 250 and 350 nm, for the same device, is reported to be D¯*=1.3×1014cmHz1/2W-1. The spatial responsivity uniformity variation was established, using H2 Lyman-α radiation, to be ±3% across the surface of a typical 0.25 cm2 diode.

Development of High-k Gates for Advances CMOS Devices High dielectric constant (high-k) materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), alumina (Al2O3), and their silicates, have drawn a great deal of attention in recent years for potential use as gate dielectrics in advanced CMOS processes [1]. With high dielectric constants, gate dieletrics can be made thicker than SiO2 while achieving the same capacitance. The result is leakage current that can be lower by as much as several orders of magnitude. However, there are still technical challenges to overcome, such as Vt instability [2-4], carrier channel mobility degradation [5-9], and long-term device reliability [10-13]. One of the important issues preventing implementation of high-k gates is the trapping of charges in the pre-existing traps inside these dielectrics [14-15]. When the transistor is turned on, some of the channel carriers will be accumulated in the gate dielectric due to the vertical electrical field, resulting in a shift of threshold voltage and a reduction in drain current. Fully understanding charge-trapping and these related mechanisms is the key to understanding channel mobility degradation and device reliability problems. However, traditional DC testing techniques may not accurately characterize these mechanisms.

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO2 dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (Vt) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on Vt.

An ultra-short pulse charge trapping characterization technique is introduced to study the charge-trapping effect in high-/spl kappa/ gate dielectrics. The system is capable of performing "single pulse" charge trapping measurement within several nanoseconds (ns) yielding near intrinsic characteristics of transistors with high-/spl kappa/ gate dielectrics with negligible charge trapping. It also characterizes transistors with high-/spl kappa/ gate dielectrics at close to operating frequency. The setup and capability of the system are described and its potential applications and benefits are discussed. We demonstrate using this technique where there appears to be no trapping with a pulse width less than 50ns and a significant increase in drive current is measured due to lack of charge trapping when comparing to DC I-V measurements for various high-/spl kappa/ gate stacks.

April 2004 1 Hunting for High k As the size of transistors continues to scale down, the use of conventional SiO2 as a gate dielectric material is approaching physical and electrical limits [1,2]. The principal limitation is high leakage current due to quantum mechanical tunneling of carriers through the thin gate oxide [3]. To reduce gate leakage current, high dielectric constant (high κ) gate materials, such as HfO2, ZrO2 and Al2O3 and their silicates [4], have drawn a great deal of attention in recent years. Due to their high dielectric constants, high k gates can be made much thicker than SiO2 while achieving the same gate capacitance. The result is lower leakage current—sometimes, several orders of magnitude lower. One of the remaining challenges of deploying high κ materials is reliability. This includes phenomena affecting material reliability, such as voltage breakdown and defect generation mechanisms, and phenomena affecting device reliability, such as hot carrier injection. To characterize the reliability of high κ gate materials fully, multiple measurement techniques are typically required. Usually, these techniques include I-V, C-V, charge-pumping, and other measurements. Various instruments can be used to take these measurements, but a fully integrated device characterization test system speeds up testing and provides a high level of data integrity. These systems typically integrate source-measure units with a C-V meter and pulse generator to characterize chargetrapping phenomena inside the high κ gate material. They can be used with various charge-trapping measurements, including a relatively new stress and charge-pumping technique that better characterizes traps in high κ films.

Pt/4H-SiC Schottky photodiodes have been fabricated with the device areas up to 1 cm/sup 2/. The I-V characteristics and photoresponse spectra have been measured and analyzed. For a 5 mm/spl times/5 mm area device leakage current lower than 10/sup -15/ A at zero bias and 1.2/spl times/10/sup -14/ A at -1 V have been established. The quantum efficiency is over 30% from 240 to 320 nm. The specific detectivity, D/sup */, has been calculated from the directly measured leakage current and quantum efficiency are shown to be higher than 10/sup 15/ cmHz/sup 1/2//W from 210 to 350 nm with a peak D/sup */ of 3.6/spl times/10/sup 15/ cmHz/sup 1/2//W at 300 nm.

A low-energy electron microscopy study of two-dimensional Si(001) island shapes near thermal equilibrium on $10\ifmmode\times\else\texttimes\fi{}15 \ensuremath{\mu}{\mathrm{m}}^{2}$ large single-domain terraces reveals a continuous increase of island aspect ratio and a shape transition from elliptical to ``American-football''-like with increasing island size. The size-dependent island shapes are driven by elastic relaxation caused by the intrinsic surface stress anisotropy present on Si(001). Analysis of the measured elliptical island shapes based on an elastic-model calculation allows a quantitative determination of step energies and of the surface stress anisotropy as a function of temperature.