计算机系统中SATA(serial advanced technology attachment)主机端控制器采用专用总线转换芯片和软件控制方式.为使得以FPGA(field-programmable gate array)为控制核心的电子系统可以直接使用SATA3.0硬盘作为数据存储介质,借鉴ATA1-7、SATA1.0、SATA2.0、SATA3.0等相关协议,提出了一种基于FPGA的SATA3.0主机端控制器的链路层发送功能模块的设计与实现方法,成功实现了数据在发送过程中的校验、加扰以及流量控制等相关功能.仿真结果表明:本控制器数据处理速度可达600 MB/s,验证了设计的正确性.

The three-phases VSR is the ideal substitution for the SCR inverter in the chopped-wave cascade speedcontrol driver,which could create the capacitive reactive power to compensate system reactive power in order toimprove the system power factor and the harmonic current to the grid.By analyzing the operation characteristics of three-phase VSR in the capacitive reactive state,basic control theory of the inverter was applied,the design methods andprinciples of applying it to chopped-wave cascade speed driver system inverter reconstruction were given.At last,theabove conclusions are verified by the Simulink simulation in Matlab.

We design a high-speed data acquisition system that uses FPGA as the main control chip, and it realizes the data communication with the PC through serial port . Each of these logic modules in FPGA is designed with Verilog HDL. By these various functional modules the system achieves high-speed analog-to-digital conversion chip control, data acquisition and processing and the communication with PC. With the use of parallel data processing ability of FPGA, compared with the traditional DSP and single-chip microcomputer as the main processing chip data acquisition system, this system can meet the high speed, high stability, high real-time requirements.

在三相电压源型SPWM整流器优化设计的研究中,利用标幺值换算的方法可以解决三相电压源型SPWM整流器在大功率应用工况时的复杂计算问题。由于测量点电量大,造成测量不准确。为此,以整流变压器阀侧额定值为基准,研究了采用直接电流控制策略时单位功率因数工况下系统参数的标幺值设计问题,给出了按照标幺值换算后各系统设计参数的修正公式,说明了整流变压器不同联接组别对整流器设定值的影响,通过仿真对该标幺值换算的方法进行了验证,为设备在较大功率应用要求时的标幺值设计提供了系统的理论依据和工程设计方法。

This paper analyzes the theory of CRC coding algorithm,calculates parallel algorithm which applies to high-speed communication,according to the traditional serial coding algorithm,ensures the logic function correctly by FPGA verification;achieves parallel CRC32coding chip design with simc18(180nm technology library).The advantages of the design is faster coding,less resource,low-power,easier to large-scale production and so on.

The focus of this paper is to decrease the noise that inpacting the ultrasonic nondestructive testing signals. Using a parallel distributed algorithm which can transfer multiply-add operations into the lookup table to design a 16-step parallel fir filter based on FPGA.The filter was simulated by Quatus II.,the hardware simulation result shows that the designed FIR filter is good and run faster.

本文深入研究SVPWM控制算法的原理,在MATLAB仿真环境下,对SVPWM算法和优化策略进行了仿真,通过Verilog硬件描述语言分别对常规模式和优化模式下的设计进行编译仿真,将在QUARTUSⅡ环境下硬件设计的编译仿真结果与MATLAB下的SVPWM仿真结果对比,验证了硬件设计方案是正确可行的

无论是在我们的生活中还是在日常生产中,节约用电都是必不可少的一个话题,本文针对节约用电问题,设计了一种单片机的照明控制系统,该照明系统属于智能控制型,对该系统的结构和功能进行研究,分析该系统的硬件和软件的组成。

In this paper,a method of designing a colored touching screen controller with FPGA is presented. A TFT-LCD controller and an interface controller of ADS7843 chip are designed in FPGA according to interface rules. The touch-enabled function on the TFT-LCD is realized in FPGA. This colored touching screen controller has a positive display effect and fast response speed. And it can be used for the design of IP core of colored touching screen.

This system uses the SoPC method to realize an isolated-word speech recognition system.The system is based on the improved DTW algorithm,and it can be easily integrated into other systems.The endpoint detection algorithm and pattern recognition algorithm are selected and modified.The speed and accuracy of the system can satisfy the needs of voice control.By SoPC technology,the system is flexible and easy to be modified for different applications.

The design is based on the DDS theory and FPGA technology.According to sequence of storage ways,we put all the sampling data of sine wave,square wave,triangle wave,and sawtooth wave in ROM waveform list.By controlling the switch and the the keyboard of external equipment,we achieve the output of the waveform needed.Eventually,the information of the waveform displays in the LCD screen.Embedded soft processor NiosⅡ program to control the coordination of each hardware module.The LCD 12864 controller in this design is an IP core realized by programming.

This paper presents an audio system with network-on-demand based on SoPC platform which is used of Nios Ⅱ softcore processor and μClinux operating system . The way of building hardware circuit and developing of application software for this system are described . The function of this system has verified with DE2-70 platform . The system is able to play local audio files and real-time network-on-demand .

The electron in the conduction channel of the GaN NMOSFET can sustain the interface scattering due to the electric field perpendicular to its direction of motion,so the characteristics of GaN NMOSFET have to be affected.In order to study the impact of the interface scattering on the transport properties of the electron,we use the bulk Monte Carlo simulation method to calculate the electronic transport properties of the wurtzite GaN with the interface scattering.The electronic transport properties of the wurtzite GaN are calculated with a horizontal electric field and vertical electric field.Due to the vertical electric field, the electron in GaN is scattered by the interface scattering mechanism.The interface scattering rates are calculated with interface roughness based on the exponential auto-covariance function.For the rms height of the amplitude of roughness and the correlation length are equal to 0.65 nm and 1.5 nm respectively and the vertical electric field is larger than 1×105 V/cm,the electron mobility decreases with the increase of the vertical electric field.The electron mobility is less than 200 cm2/(V·s) for the vertical electric field is larger than 1×106 V/cm.Compared with the study of the electronic transport properties with interface scattering using MOS structure,this method excludes the factors of non-uniform electric field of the channel of MOS structure and unsteady-state.

This paper presents a design of 2-D DCT IP soft core based on Loeffler′s algorithm.We make use of the shifter and addition operations to replace the multiplication operations.In order to save hardware resources,the multiplication factors are coded by CSD,and the technology of 1-D DCT reusing is taken;In order to improve the circuit speed,the pipelining technology is taken,and optimize the transposed matrices is adopted.Based on above-mentioned algorithms the IP soft core with Verilog HDL is obtained.For the IP soft core,we made the compiling,synthesis,layout and post simulation,so the correctness of the design is verified.The experiment shows that design has a maximum frequency of 139.43 MHz,which can satisfy the requirement of real-time video image compression.

Traditional ECRL(Efficient Charge Recovery Logic) adiabatic circuit has two disadvantages.One is that the energy of the circuit nodes can not be completely recycled ;The other is that the power consumption is rapidly raised with the increase of load capacitance.Two improved circuits overcoming two disadvantages are proposed.One is to construct an energy recovery path,through which the energy un-recycled is recovered to achieve full recovery with limited non-adiabatic adiabatic energy loss.The other is to make the non-adiabatic process of the circuit associate with only the smaller MOSFET gate capacitance instead of the load capacitance by a bootstrap operation.The HSPCIE simulation with 0.5 μm BSIM3v3 model technology proves that the power consumption of the two improved circuit has a certain degree of reduction compared to ECRL circuit.

This paper introduced a low-voltage low-power amplifier based on the bulk-driven technique.Bulk-driven MOSFETs at the inputs avoid the limitation of threshold voltage efficiently.A feed-forward class AB output stage is used to ensure that the current of the output transistors is controlled precisely and the output swing reaches rail-to-rail.The circuit is designed by using predictive technology model 0.18 μm CMOS and simulated by Hspice software.The simulation results show that the DC gain is 62.1 dB,the unity gain bandwidth is 2.13 MHz,and the phase margin is 52°,the circuit operates normally in a low voltage of 0.8 V and the power consumption is only 65.9 μW.

为提高工科研究生的培养质量,以大电子类硕士研究生的课程建设为例,提出跨学科学习计划,改变以二级学科设置研究生课程的常规教学体系,探讨一、二级学科相结合的课程体系设置方式。

We present the results of the electron transport property in wurtize GaN using an ensemble full band Monte Carlo simulation. The data of wurtzite GaN band structure calculated with the first-principles total-energy pseudopotential method is used in the simulations. The impact ionization scattering rate is calculated based on Cartier’s method. The average electron drift velocity and the average electron energy each as a function of electric field are computed. The electron impact ionization coefficient is calculated as a function of applied electric field. The analysis of the impact ionization coefficient shows that when the applied electric field is greater than 1 MV/cm, the obvious impact ionization events occur. The analysis of the quantum yield shows that when the electron energy is greater than 7 eV, the quantum yield increases rapidly with electron energy increasing. We study the occupancy of the electrons in the eight conduction bands at the applied electric field ranging from 0 to 4 MV / cm. For the case of the low applied electric field all of the electrons are located in the 1st conduction band. With the increase of the applied electric field, some of the electrons move to high index conduction bands. For the whole range of the applied electric field, most of the electrons are located in the 1st conduction band and 2nd conduction band, a small number of the electrons are located in the 3rd, 4th and 5th conduction band, and very few electrons are located in the 7th and 8th conduction band.

Combination of the characteristics of electronic and information technology development and the requirements of the ability and quality of the talents in electrical information for our national electronic information industry,we propose a framework of practical teaching system,in which a project-based practical module,two main lines of discipline-based practical module,three EDA levels of education modules,and four kinds of Embedded practical modules.This framework is the basic summary of the current public practical teaching system for the undergraduate majors of electrical information,reveals the inherent rules among the various practical links,so it can play the role of reference and guidance in the development of training programs.

A novel domino XNOR gate is designed, using techniques of pn mixed pull-down network and dual-threshold voltage. HSPICE simulation results prove that compared with the standard n-type domino XNOR gate the dynamic power of proposed design can be reduced by 43.9% and the minimum static power is reduced by 86.4%, while enhancing the AC noise immunity by 12.5%.