The combination of antennas-array and advanced signal processing technology leads to the appearance of smart antennas,which have the capability of concurrently dealing with signals of space domain and time domain.Research on smart antennas has become a hot spot in the area of signal processing.Currently,in TD-LTE systems,the multi-antennas beamforming technology with tiny array distance is applied to base station(BS),in order to lower the intra frequency interference between different user equipments(UE),and to increase the throughput of the UE in the edge of the cells,and enlarge the range of coverage of the cells.To grantee the accuracy and reliability of beam shaping,the adjusting of antennas-array has become a key technology,which can reduce the amplitude errors and phase errors of different tunnels of the arrays.The simulation results show that our proposed scheme grantees the accuracy and reliability of beamforming.

A 6th-order programmable fully differential Chebyshev low-pass filter for 860-960 MHz UHF RFID reader was implemented based on TSMC's 0.25μm RF CMOS process.A fully balanced differential difference amplifier using common-mode feedback(CMFB)strategy was employed in this circuit.Circuit simulation showed that the cut-off frequency of the filter could be controlled to 400 kHz、600 kHz、800 kHz、1000 kHz and 1.3 MHz by a 3bit controller,and a spot noise of 20 nV/(Hz)~(1/2)at 1 MHz and 1 dB input compression point of 15 dBm were achieved for the circuit,which dissipates 4.86 mA of current from a single 3.3 V power supply.

A novel pipeline ADC structure based on MATLAB/Simulink toolbox is proposed.In order to balance higher power dissipation in 4 bit first-stage architecture and lower precision in 2 bit per-stage structure,a 8-stage type with 3 bit first stage is introduced. Simulation results indicate that the maximum SNR(Signal to Noise Ratio) and SFDR(Spurious Free Dynamic Range) of this ADC(Analog to Digital Conversion) are 60.6 dB and 82.177 dB respectively, with the input signal frequency of 10 MHz and sampling clock of 40 MHz. The model of novel pipeline ADC can give helpful information on improving system error performance and research on system static characteristic.

A ZBT SRAM controller and a bus arbitrage strategy have been designed according to the requirement of fingerprint recognition system based on ASIC(Application Specific Integrated Circuit).This controller provides an interface between FPGA and ZBT SRAM,realizing seamless transaction of data stream.It also provides a data storage method which is suitable for the pipeline algorithm required by fingerprint recognition system.The designed modules have been verified by Xilinx Virtex 4 FPGA and achieve the functional and timing requirements of the ASIC chip.

This paper introduces a method for optimizing FPGA code.By synthesis tool in QuartusII,the optimized code could be synthetized to Magefunctions which make use of Memory Bits instead of LEs.