With the continuous advancement of Terahertz radar technology, high-resolution, high-definition and real-time Terahertz near-field imaging has emerged as a new research objective. However, due to the radar’s high-speed motion and the accompanying mechanical vibrations, significant motion errors are induced, which in turn substantially deteriorate the imaging quality. Conventional studies often simplify vibration to a sinusoidal model, but this assumption may not fully reflect real-world conditions. This paper proposes a more realistic perturbation model and a motion compensation scheme based on STFT and PGA, which can better address nonlinear problems. Through actual experiments and ablation studies, this paper demonstrates that this method has the advantages of fewer iterations and better imaging quality. Under the same image contrast, the algorithm proposed in this paper only requires 3 iterations. The PSNR of the imaging results of the algorithm proposed in this paper increases by approximately 3 dB.

Conventional management of type-1 diabetes (T1D) relies on finger-prick blood sampling or electrochemical methods, which prevent continuous monitoring and treatment. This paper presents a novel epidermal pasting bioelectronic device (PBD). The device integrates a 19fA-resolution bioluminescence analog front-end (BAFE) with TDM-SAR calibration and a hybrid-mode LED driver. It enables closed-loop realtime detection and precision treatment for T1D. The battery life reaches 48 days.

This paper presents a compact broadband and high-efficiency power amplifier (PA) for fifth-generation (5G) new radio (NR) frequency range 2 (FR2) communications. Using a class-B PA as an example, the mechanism behind inherent power-added efficiency (PAE) non-flatness in conventional cascode architectures is analyzed. To address this, the design incorporates a parallel inter-stage inductor, which effectively mitigates non-ideal effects in traditional cascode structures. The proposed architecture improves the output impedance matching, resolving the degraded S22 performance in conventional cascode PAs at saturation power (Psat). This enhancement makes the design more suitable for phased-array applications. Furthermore, a compact low-coupling transformer is implemented to minimize chip area. Designed in a 40 nm CMOS, the PA achieves 19.27 dBm Psat with a 3 dB bandwidth spanning 21–38 GHz. Within 22.5–38 GHz, the Psat variation remains below 1 dB. The PAE variation is maintained within <1% from 24–36 GHz. The core area occupies only 0.089 mm2.

FMCW radar is widely used in the field of autonomous driving. However, the high-resolution signal processing in FMCW radar presents challenges for on-chip memory and transmission bandwidth. Thus, We propose a compression method that integrates a lattice vector quantization scheme with non-uniform amplitude quantization, while employing uniform quantization for phase. During amplitude quantization, the algorithm first performs grouped quantization on spectral data to mitigate the impact of high-amplitude values on quantization accuracy. It then applies vector normalization to reduce the hardware resources required for storing shared parameters, and selects the quantization approach based on the numerical distribution characteristics. All modules are implemented with hardware-friendly operations to strike a balance between efficiency and feasibility. The experimental results demonstrate that our algorithm achieves a 74.8% reduction in storage usage while maintaining a reconstructed signal PSNR of 40 dB, and requires only a minimal amount of additional computational resources to ensure its object detection performance.

With the continuous advancement of millimeter-wave (mmWave) radar technology, high-resolution, high-definition and real-time near-field imaging has emerged as a new research objective. However, existing near-field SAR imaging approaches still face numerous challenges. Achieving high-resolution imaging requires optimizing and enhancing radar bandwidth, data acquisition density, and scanning aperture. This, in turn, imposes higher demands on processing speed and parallelism for computational units to enable real-time imaging capabilities. In this paper, we propose a novel multiscale decomposition imaging acceleration strategy based on the wavelet transform, which achieves parallel acceleration across multiple units while reducing the computational cost. By comparing imaging results between this method and previous algorithms using metrics such as SSIM and Jaccard, we demonstrate high-precision, rapid radar imaging of two-dimensional planes with minimal compromise in imaging quality.

This paper presents an ultra-low-power, high-output-power, and high-sensitivity transceiver for implantable bioelectronic systems in a 40-nm CMOS technology. The design targets stringent power constraints by employing a wake-up scheme. The transceiver introduces a transmitter architecture based on a cascaded injection-locked ring oscillator (ILRO) and edge combiner (EC), alongside a receiver utilizing an envelope-detection demodulation technique for power reduction. The switched-capacitor power amplifier (SCPA) enables high output power through its high-efficiency characteristic, while a high-gain low-noise amplifier (LNA) ensures high-sensitivity reception. Compared with prior works, this transceiver achieves simultaneous high output power and high sensitivity within an ultra-low-power architecture, making it ideal for implantable bioelectronic applications. The proposed techniques reduce sleep-mode power consumption to 40 nW. The transmitter delivers 2.37-dBm output power with 8.2-mW consumption, and the receiver attains –64-dBm sensitivity with 200-µW consumption over a 10-meter wireless range.

Conventional management of type-1 diabetes (T1D) relies on finger-prick blood sampling or electrochemical methods, which prevent continuous monitoring and treatment. This paper presents a novel epidermal pasting bioelectronic device (PBD). The device integrates a 19fA-resolution bioluminescence analog front-end (BAFE) with TDM-SAR calibration and a hybrid-mode LED driver. It enables closed-loop realtime detection and precision treatment for T1D. The battery life reaches 48 days.

This article presents a 20-25-GHz low-noise amplifier (LNA) based on a transformer-assisted improved multipath noise-canceling (IMNC) architecture. The proposed approach addresses key limitations of the conventional dual-path noise-canceling (DPNC) technique, which utilizes common-source (CS) and common-gate (CG) stages to suppress each other's noise. In the DPNC topology, noise from the CG stage is not fully eliminated, and increasing the CG transistor's transconductance to enhance CS-stage noise cancellation introduces a tradeoff between noise performance and power consumption. To overcome these limitations, the IMNC architecture utilizes a three-coil transformer to boost the CG stage gain, thereby improving the CS noise cancellation without additional power consumption. Furthermore, the transformer introduces an auxiliary noise-canceling path that enables partial self-cancellation of the CG stage noise. These enhancements result in improved noise performance and power efficiency compared to the conventional DPNC approach. Fabricated in a 40-nm CMOS process, the proposed IMNC-based LNA achieves a peak gain of 14.5 dB, a 3-dB bandwidth of 5.1 GHz spanning 19.9-25 GHz, and a minimum noise figure (NF) of 2.0 dB, while consuming 22.4 mW of power and occupying a core area of 0.16 mm(2).

This article presents a Doppler-assisted frequency-modulated continuous-wave (FMCW) radar that combines precise range resolution capability of FMCW with high sensitivity of Doppler radar, enabling versatile performance for indoor applications. A comprehensive analysis of low-frequency noise contributions from key receiver (RX) blocks including low-noise amplifier (LNA), mixer, local oscillator (LO) buffer, and analog baseband (ABB) circuits is conducted. An “RF+LO+BB” joint noise figure (NF) improvement method is proposed to effectively suppress the low-frequency noise. To minimize frequency modulation (FM) error in charge-pump-based fractional-N phase-locked loops (PLLs), a nested-PLL architecture with an optimized loop parameter selection method is employed, significantly enhancing chirp linearity. Fabricated in a 55-nm CMOS technology, the proposed Doppler-assisted FMCW radar achieves NFs of 32.13 and 12.94 dB at 10 Hz and 1 kHz, respectively, and a chirp linearity of 0.0039% over a 3.52 GHz chirp bandwidth (BW), resulting in a maximum detection range of 19.41 m and a range resolution of 4.7 cm. The radar occupies a die area of 12.7 mm2 and consumes 594 mW in FMCW mode and 432 mW in Doppler mode under a 3.3 V supply.

This letter presents a integer-N quadrature oversampling phaselocked loop (QOPLL) operating at 5.76-6.48 GHz with low RMS jitter. The QOPLL features a calibration-free gain-boosting quadrature oversampling mechanism. The proposed gain-boosting quadrature oversampling mechanism addresses the incompatibility issues in conventional oversampling mechanisms and gain-boosting techniques. It enhances in-band phase noise performance while eliminating the need for phase detector gain calibration. An isolated reference sampling phase detector (IRSPD) has been developed to ensure quadrature phase accuracy and improve phase detector gain. The QOPLL is fabricated in a 40-nm CMOS process. Measurement results demonstrate an RMS jitter of 103 fs, integrated from 10 kHz to 100 MHz. The reference spur is-71.26 dBc. The power consumption is 15 mW.

This paper presents a high-linear ity millimeter-wave (mmWave) Doherty power amplifier (PA) for 5G FR2 wireless communications. A precise mutual distortion cancellation (PMDC) method for parallel Doherty PA is proposed. The auxiliary path current amplitude is adjusted by the common-source common-gate (CSCG) dual adaptive bias circuit (DADB). Meanwhile, the main path current phase is tuned by the phase nonlinear compensation capacitor (PNCC). These two techniques are combined to enable precise distortion cancellation, thereby optimizing the Doherty PA's AM-AM and AM-PM distortions. The chip is fabricated in a 40 nm CMOS process. The measurement results show that the proposed Doherty PA achieves a small-signal gain of 19.6 dB, a 3-dB bandwidth from 21 to 29 GHz, a saturated output power (Prat) of 19.1 dBm, an output 1-dB compression point (OP1dB) of 17.9 dBm, a peak power added efficiency (PAEpeak) of 22.7%, a power added efficiency at 6-dB power back-off (PAE-6dB) of 15.1%, and an AM-PM distortion of 0.93 degrees at 26 GHz. When using a 64-QAM 100 MHz OFDM modulated signal as the input, which meets the 5G NR FR2 communication protocol and has an input PAPR of 11.38 dB, the measured output EVM is-25 dB, and ACLR is-30.5 dBc. The proposed PA realizes an average output power (Pavg) of 12.6 dBm and an average power added efficiency (PAEavg) of 11.3%.

This paper presents an image-reused phase tuning technique (IPTT) for millimeter-wave (mm-wave) quadrature voltage-controlled oscillators (QVCOs). The phase shifter addresses the -45 degrees-45 degrees phase rotation limitation, extending it to 135 degrees.-225 degrees. This enhancement extends the QVCO tuning range without deteriorating phase noise. To facilitate the expanded phase tuning range, a transformer-based fourth-order resonator providing bimodal impedance is employed in the proposed QVCO. The bimodal impedance ensures intra-band monotonicity and inter-band continuity, optimizing the overall tuning range. Mismatch mitigation and PLL integration of the proposed QVCO are also discussed. A prototype QVCO, operating from 31.6 to 49.2 GHz, is fabricated in a 40-nm CMOS process. Measurement results show that the QVCO consumes 10 mW of power and achieves a tuning range of 44% and phase noise of -129 dBc/Hz at 10-MHz offset. This leads to a figure of merit (FoMT) of -204 dBc/Hz at a 10-MHz offset.

Cost aggregation is a crucial step in the accurate stereo depth estimation process known as semi-global matching. However, this step is challenged by storing large amounts of aggregated data, which is necessary to achieve high matching accuracy under large resolution and large disparity conditions. In this paper, we propose a multi-path optimization aggregation strategy and re-select the complementary combinations of key paths in the forward and backward scanning directions to improve the matching accuracy as much as possible. An error rate of only 5.21 degrees 7 degrees is achieved on the KITTI 2015 dataset. Next, we propose DCT-based truncated compression and selective storage to alleviate the problem of memory increase due to the introduction of reverse critical aggregation paths. Experiments show that the matching error rate increases by only 0.6 degrees 7 degrees on the KITTI 2015 dataset with 53 degrees 7 degrees memory savings. Finally, 1920 x 1080 @62fps @128MHz is achieved on ZCU102 FPGA.

This article presents a fully integrated 77-GHz hybrid time-division-multiplexing multiple-input-multiple-output (TDM-MIMO) phased-array radar in a 55-nm CMOS process. The system integrates eight independent transmitters ( 8 x 1 TXs) and two four-channel phased-array receivers ( 2 x 4 RXs), achieving a 4.76x increase in detection range compared to single-input-single-output (SISO) architecture in long-range radar (LRR) mode and 1.79 degrees angular resolution with 16x4 virtual array in short-range radar (SRR) mode. To realize a large chirp bandwidth while maintaining low voltage-controlled oscillator (VCO) gain ( K-VCO ), a zig-zag phase-locked loop (PLL)-based frequency-modulated continuous wave (FMCW) generator is proposed, enabling continuous multi-subband chirping. By monitoring the voltage across the capacitance in loop filter ( V-CAP ) for subband switching, the tuning voltage ( V-TUNE ) is configured to the optimal switching voltage, eliminating the frequency ripple ( F-R ) during subband switching. Each TX channel integrates switches to support a flexible number and positioning of 1-8 transmitters in TDM mode. To mitigate the leakage effect caused by variations in amplitude and phase due to the varying number and position of TX on-channels, a receiver architecture with three low noise amplifiers (LNAs) and a 4-bit phase shifter is designed to achieve low noise figure (NF) and high linearity. Furthermore, an I/Q mixer is designed to achieve orthogonal-ellipse-overlapping-shape NF and petal-shape linearity over a phase difference range of 0 degrees- 360 degrees Delta phi(leak) between the local oscillator (LO) and leakage. The chip achieves a measured maximum chirp bandwidth of 12.6-GHz spanning four zig-zag subbands. The root-mean-square (rms) frequency error is 0.0068% at 18.8-MHz/ mu s chirp rate with 2.5-GHz bandwidth, and 0.3% at 545-MHz/ mu s chirp rate with 2.65-GHz bandwidth. The eight-channel TX achieves a maximum effective isotropic radiated power (EIRP) of 32 dBm at 78.8 GHz, while the four-channel RX achieves a minimum NF of 16.3 dB at a 2-MHz intermediate frequency (IF). The hybrid radar achieves a detection range of 186 m and a range resolution of 3 cm.

This paper presents a fully-integrated dual-mode switchedcapacitor (SC) DC-DC converter to supply always-on wake-up timer in biosensor systems. To balance chip area and conversion efficiency, optimal sizes of power switches, flying capacitor (Cfly) and output capacitor (Cour) in SC cell are determined through power loss analysis method. Power-on and self-powered modes (dual modes) under two voltage domains and an on-chip ultra-low-power (ULP) bias circuit are proposed to further improve the conversion efficiency. Furthermore, a hybrid selfbiased current (HSBC) scheme is utilized to achieve low output voltage ripple. Implemented with a 40-nm CMOS process, this DC-DC converter can realize the voltage conversion from 1.8 V to 0.4 V. Measurement results show that the peak conversion efficiency reaches 75 % at average load arriving 3 mu A, while the voltage ripple is below 12 mV over 10 nA-5 mu A load range.

This paper presents a transformer-based improved multi-path noise-canceling (IMNC) low noise amplifier (LNA) for K-band satellite communications. The design enhances the dual-path noise cancellation and significantly reduces the noise figure. The proposed LNA employs a three-coil transformer with dual-eight-shaped inductor to boost gain, and introduces a noise cancellation path for the common-gate transistor to optimizes noise performance. During the circuit design phase, a multicomponent integrated modeling (MIM) technique is applied, which accurately characterizes the EM field of the LNA and ensures high consistency between simulation and measurement results. The LNA, fabricated in a 40 nm CMOS process, consumes 28.8 mW of power and achieves a peak gain of 12.6 dB. Its 3-dB bandwidth ranges from 19.9 to 25 GHz with a minimum noise figure of 2 dB. The core area of the LNA is 0.16 mm(2).

The traditional RC delay model and the small-signal model do not suffice for a precise analysis of the dynamic current mode logic (DCML) divider in the millimeter-wave (mmW) frequency band. This paper explores the current vector model and examines the prerequisites for the proper functioning of the DCML, including phase, gain, and amplitude aspects, using expressions and vector diagrams as references. To fulfill the frequency division requirements of mmW ultra-wideband phaselocked loops, a broadband DCML4 divider has been designed based on the aforementioned analysis. Simulation results show that with an input power of -4 dBm, the maximum frequency division range for a single sub-band can reach up to 137.5% (from 5 to 27 GHz). The center frequency is adjusted via biasing, enabling the total frequency coverage to achieve 150% (ranging from 5 to 35 GHz). At a supply voltage of 1.2 V, the average power consumption is only 6.72 mW.

This paper presents a Doppler-assisted frequency modulated continuous wave (FMCW) radar that leverages the benefits of FMCW's range resolution and Doppler's sensitivity for indoor applications. The Doppler mode reuses circuit blocks in the FMCW mode to reduce power consumption and area overhead. Low-frequency noise contributions from the receiver circuits are analyzed and an "RF+LO+BB" combined noise figure (NF) optimization scheme is proposed to minimize the low-frequency noise. The radar employs a nested phase-locked loop frequency synthesizer with low phase noise and incorporates an optimized Delta T-step selection technique to improve chirp linearity. Designed in a 55-nm CMOS technology, the radar achieves NFs of 32 dB and 12 dB at 10 Hz and 1 kHz, respectively, and a chirp linearity of 0.0039% over a 3.52 GHz chirp bandwidth (BW), leading to a range resolution of 4.7 cm. The radar occupies an area of 12.7 mm(2), and consumes 220 mA of current in the FMCW mode and 160 mA in the Doppler mode under a power supply of 3.3 V.

This paper presents a 3.5-7.2 GHz wideband front-end module (FEM) implemented in 22-nm CMOS technology. The FEM consists of a digital power amplifier (DPA) and a low noise amplifier (LNA). The DPA utilizes a 4-way balanced-power-combining (BPC) network with electrical coupling compensation to minimize broadband amplitude modulation (AM) and phase modulation (PM) mismatches among the four sub-arrays. To improve efficiency and linearity, an AM-PM distortion-canceling power cell is developed. The LNA employs a dual-resonant input matching (DRIM) approach to achieve wideband input impedance and noise matching. The DPA achieves a peak output power of 30.08 dBm with a drain efficiency of 43.31% at 6 GHz. For a 40 MHz 256-QAM signal, the average output power (P-avg) is 19.09, 21.07 and 17.18 dBm at 4.5, 6, and 7.2 GHz, respectively, with average drain efficiency (DEavg) of 20.39%, 20.6% and 18.5%. For a 20 MHz 1024-QAM signal, the P-avg is 16.7, 18.25 and 17.55 dBm at 4.5, 6 and 7.2 GHz with DEavg of 18.22%, 18.41% and 16.53%, respectively. The LNA achieves a peak S21 of 18.8 dB at 6 GHz, with the noise figure (NF) of 1.7 dB and S11 and S22 below -10 dB across the 3.5-7.2 GHz range.