Deep Neural Networks (DNNs) are the primary approach for enhancing the real-time performance and accuracy of Keyword Spotting (KWS) systems in speech processing. However, the exceptional performance of DNN-KWS faces significant challenges related to computational intensity and storage requirements, severely limiting its deployment on resource-constrained Internet of Things (IoT) edge devices. Researchers have sought to mitigate these demands by employing Binary Neural Networks (BNNs) through single-bit quantization, albeit at the cost of reduced recognition accuracy. From an information-theoretic perspective, binarization, as a form of lossy compression, increases the uncertainty (Shannon entropy) in the model’s output, contributing to the accuracy degradation. Unfortunately, even a slight accuracy degradation can trigger frequent false wake-ups in the KWS module, leading to substantial energy consumption in IoT devices. To address this issue, this paper proposes a novel Probability Smoothing Enhanced Binarized Neural Network (PSE-BNN) model that achieves a balance between computational complexity and accuracy, enabling efficient deployment on an FPGA platform. The PSE-BNN comprises two components: a preliminary recognition extraction module for extracting initial KWS features, and a result recognition module that leverages temporal correlation to denoise and enhance the quantized model’s features, thereby improving overall recognition accuracy by reducing the conditional entropy of the output distribution. Experimental results demonstrate that the PSE-BNN achieves a recognition accuracy of 97.29% on the Google Speech Commands Dataset (GSCD). Furthermore, deployed on the Xilinx VC707 hardware platform, the PSE-BNN utilizes only 1939 Look-Up Tables (LUTs), 832 Flip-Flops (FFs), and 234 Kb of storage. Compared to state-of-the-art BNN-KWS designs, the proposed method improves accuracy by 1.93% while reducing hardware resource usage by nearly 65%. The smoothing filter effectively suppresses noise-induced entropy, enhancing the signal-to-noise ratio (SNR) in the information transmission path. This demonstrates the significant potential of the PSE-BNN-FPGA design for resource-constrained edge IoT devices.

Analog-to-information converters (AICs) provide sub-Nyquist sampling rates by signal bandwidth compression, leading to continuous charge accumulation within the circuit. The amplitude of the compressed signal sometimes exceeds the voltage range of the circuits, thereby impacting its precision. The incorporation of voltage boosting and interpolation into flash AIC is suggested to resolve this problem. A voltage boost method with a charge pump generates several reference levels for a comparator. The output of the comparator is subsequently segmented and quantified by hybrid domain quantization, resulting in an interpolated digital sequence. The experimental results demonstrate that the proposed flash AIC is capable of processing a signal with an amplitude range of 1 V while operating on a supply voltage of 0.8 V. It samples the signal at a maximum bandwidth of 25 MHz, at a rate of 12.5 MHz, and achieves 4-bit quantization through the use of a 1-bit comparator. Compared with the current AIC designs, the flash AIC achieves a 2x improvement in the Figure of Merit (FoM), while incurring only a negligible compromise on the reconstructed signal-to-noise ratio (RSNR).

Compressive sensing (CS) theory states that sparse signals can be sampled at a sub-Nyquist rate without information loss. The combination of CS and analog-to-digital converter (ADC) has demonstrated an effective reduction in the conversion rate. However, the majority of prior CS ADCs have not been successful in efficiently optimizing the quantization process. This paper proposes the predictive quantization method for the CS successive approximation register ADC. This approach not only reduces the conversion rate but also decreases the number of conversion bits. The pseudo-random sequence used in random demodulation, along with the previous value, serves as the basis for prediction to address the challenge that results from the randomness by mixing. With predictive quantization, the reduction in the number of bits per conversion contributes to improving overall power saving. The prototype circuit is designed in a 0.18-µm CMOS process. The simulation results indicate that the proposed ADC successfully reduces the average number of conversion bits to 6.97 bits for ECG signals when the resolution of ADC is 10 bits. There is approximately a 30

Lensless imaging has gained popularity in various applications due to its user-friendly nature, cost-effectiveness, and compact design. However, achieving high-quality image reconstruction within this framework remains a significant challenge. Lensless imaging measurements are associated with distinct point spread functions (PSFs), resulting in many PSFs introducing artifacts into the underlying physical model. This discrepancy between the actual and prior models poses challenges for standard reconstruction methods to effectively address high-quality image reconstruction by solving a regularization-based inverse problem. To overcome these issues, we propose MN-FISTA-Net, an unrolled neural network that unfolds the fast iterative shrinkage/thresholding algorithm for solving mixed norm regularization with a deep denoiser prior. Our method enhances mask-based lensless imaging performance by efficiently addressing noise and model mismatch, as evidenced by significant improvements in image quality compared to existing approaches.

Wi-Fi imaging achieves object perception in the form of images by analyzing Wi-Fi signals and their channel response. To solve the modeling problem of Wi-Fi imaging, a method based on Wi-Fi electromagnetic diffraction tomography is proposed. Firstly, the Wi-Fi communication system is mathematically modeled, which contains a channel model and channel state information(CSI) indicator, and the CSI matrix of the Wi-Fi system is highlighted. Secondly, the electromagnetic diffraction tomography physical model and its mathematical principles are analyzed, and the imaging algorithm is proposed. Then the hardware platform of the system was built, and the software modification and debugging were carried out. Finally, the CSI was acquired by this hardware system, and this data was processed, including the removal of outliers, noise reduction, and phase correction, and subsequently reconstructed into a clearer contour map by the Wi-Fi electromagnetic diffraction tomography algorithm.

The development of the novel theory of unlimited sampling (US) has enabled analog-to-digital converters (ADCs) to effectively manage input signals with dynamic ranges that far exceed the threshold voltage. However, the existing design of the US asynchronous sigma-delta modulator ADC (US-ASDM-ADC) employs a nonlinear modulo operation within a two-channel architecture to generate the remainder and integer parts, leading to significant amplitude loss due to non-ideal phenomena. To address this issue, we propose a novel single-channel architecture and feedback compensation mechanism for the US-ASDM-ADC. Our approach entails a single-channel folding module to generate the remaining modulo operation while simultaneously generating the integer part of the modulo operation and initiating amplitude correction via a Schmitt trigger-based feedback system. We validate our proposed approach through transistor-level simulations.

为了适应新型物联网设备对于小体积的要求,提出一种基于无镜头成像的检测分类方法.基于摄像头的计算机视觉处理任务目前已可集成到各种硬件设备中,然而随着物联网技术的快速发展,笨重的镜头已无法满足小体积的要求.无镜头成像技术是一种新型成像技术,其通过编码掩膜取代传统相机镜头而大大减小了相机体积和成本.本文通过分析无镜头成像基本原理与图像重构方法,并将其与神经网络联合,实现了基于无镜头成像的目标检测分类.实验使用VGG19 网络进行了测试,证明了该方法的可行性.

得益于无线通信以及数据科学的飞速发展,物联网智能终端拥有了无源感知的能力.Device Free Localization(DFL)是一种重要的无线电无源感知技术之一,十多年来已经有大量研究,具有广阔的发展前景.基于RSSI的射频层析成像(RTI)方法因其成本低、部署方便等优点备受关注.然而,需要大量的观测样本是目前无线电层析成像难以实现实时成像的主要原因.利用压缩感知技术虽然可以有效降低RTI所需观测向量的数量,但是由此导致RTI性能急剧下降,难以满足无设备定位的应用需求.针对这一问题,本文构建了基于菲涅尔区的无线电传输经验模型,预先确定受目标影响的无线链路,极大减少了采集系统的样本数,提高了成像的实时性.实验结果表明,本系统将样本数减少至8.42%左右,仍然能够保持高定位精度.

The orthogonal matching pursuit (OMP) has been widely explored to realize real-time compressed sensing (CS) reconstruction. The matrix pseudo-inverse of the least squares (LSs) is the most computationally complex operation in the OMP. Among various algorithms to realize this complex operation, the alternative Cholesky decomposition (ACD) algorithm performs the best. However, it typically involves a very long computation time due to its iterative procedure. To accelerate the ACD-OMP algorithm, a novel method called clustered computing look-ahead (CCL) is proposed. Inspired by the famous parallel carry look-ahead adder (CLA), CCL adds a propagation matrix to decouple the data dependency in ACD and then uses a clustering operator to transform the iterative computation of ACD into a pipelined and parallelized computation. This brief also proposes an efficient hardware architecture of the CCL-based ACD-OMP algorithm for CS reconstruction. The proposed algorithm is implemented on field programmable gate array (FPGA). For sparse signals with the same sparsity and length, the proposed implementation is 1.96 times faster than state-of-the-art work.

Along with the rise of edge computing (EC), the cooperation of EC nodes becomes critical, which fuels a growing demand for inter-EC-node (inter-ECN) transfers. Typically, data are transferred in an end-to-end (E2E) manner. However, bulk data, tight transfer deadline and bandwidth fragmentation make such transfers extremely difficult. In this paper, we incorporate multi-path routing and storage on EC nodes into the data transfer, and present an edge-storage-aided multi-path scheduling method (ESMP) for inter-ECN transfers across the EC-enabled optical metro network. ESMP splits the data into chunks and schedules them across link-disjoint routing paths with the help of EC storage. Specifically, within the same deadline for the whole data, a chunk can tolerate longer storing delay and hence can be temporarily stored on an intermediate EC node when its next hop is busy. As a result, a routing path can be split into time-independent sub-paths when the E2E provisioning fails. This improves both the throughput and the flexibility of each transfer. Besides, ESMP can dynamically adapt multi-path routing to balance the completion time and the bandwidth usage based on the current network state. Studies show that compared with the existing scheduling methods, ESMP can accommodate more transfers while reducing the completion time.

In this paper, we propose a novel sensing matrix design for the pulse-width modulation (PWM)-based analog-to-information converter (AIC), which obtains the digital feature of an analog signal rather than its sparse coefficients. The method firstly selects feature subsets by feature selection algorithm of support vector machines (SVMs) and then establishes the relationship between feature subsets and the vector of sensing matrix of PWM-based AIC. Then, a sensing matrix with a higher compression ratio can be obtained. The new optimized sensing matrix is mapped to the reference modulation sequence of the PWM-based AIC’s modulation signal to obtain the PWM-based analog-to-feature converter (AFC). Experimental results show that the PWM-based AFC can reach 99.40% accuracy even when the compression ratio is higher than that of other literature.

A low-complexity iterative hard thresholding (IHT) algorithm-based detector is proposed for the compressed orthogonal frequency division multiplexing with index modulation (OFDM-IM) system. To improve recovery accuracy and reduce the number of iterations, detection is embedded into the iterations of the IHT algorithm, and the block energy information is used to identify subblocks that are more likely to be error-recovered. Compared with the existing methods for improving spectral efficiency, the new method does not expand the detection search space and not need extra pseudo-inverse calculations during iterations. Theoretical and simulation results show that the proposed scheme can considerably reduce computational complexity while improving spectral efficiency and preserving significant BER performance gain.

有限新息率(Finite Rate of Innovation,FRI)采样利用已知的信号波形结构实现信号的亚奈奎斯特率采样,在宽带信息系统应用中具有广泛的前景.但是,在实际的信息系统中,信号波形结构常常因噪声、远距离传输等非理想因素而发生畸变,从而导致FRI重构失败.本文依据波形再生的原理,提出了一种基于长短时记忆(Long and Short-Term Memory,LSTM)自动编码器的FRI重构方法.该方法利用LSTM自动编码器取代FRI采样系统中的采样核函数,通过离线训练获取畸变信号的未知波形结构,从而将波形序列投影为狄拉克特征序列,实现了波形畸变信号的FRI采样及重构.结果表明,本文的方法可以借助经典的零化滤波器有效地重构由于多径效应而发生畸变的FRI波形信号.

正交匹配追踪(Orthogonal Matching Pursuit,OMP)算法是压缩感知系统中应用最广泛的重构算法之一.OMP算法中的最小二乘(Least Squares,LS)问题涉及到矩阵求逆运算,是计算复杂度最高的部分.本文提出了一种近似OMP算法,通过优化最小二乘问题提高重构速度,更利于硬件实现.设计了一种基于FPGA的近似OMP算法的硬件实现架构,主要包含计算模块、存储模块和控制模块3个部分,利用Xilinx公司的Vivado软件进行综合仿真实验.对比现有相似实现设计,本文设计的架构通过调用更多的DSP资源减少了slices资源的使用量,在208MHz频率下重构速度提升了1.25-1.72倍,同时具备一定的可扩展性.

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems.

在过去的几年中,WiFi的应用已经非常普遍.将其应用在对人的定位上是研究的主流趋势,其原理是WiFi信号辐射某个区域时,会有自己的信道和频率.目前,实现室内定位过程较为复杂,首先是确保是离线状态,其次是构建一定的特征库,并且还要考虑设备的兼容性.文章给出了一种新的定位系统,通过WiFi信号获取人体的数据,并对数据做一定的分离,最后根据参数确定人体的具体位置.

This paper designs and implements a dedicated microprocessor architecture based on the RISC-V (the fifth-generation Reduced Instruction Set Computing) with only 20 instructions for arbitrary-point FFT (Fast Fourier Transform) algorithm. Moreover, the corresponding SoC (System-on-Chip) is also built for the expansibility and reconfigurability. The methodology of software and hardware co-verification is applied to validate the correctness of the systematic functions by comparing the simulation results between MATLAB, Visual Studio 2019 and VIVADO 2019.1. Finally, the Xilinx Artix-7 (XC7A100TFGG484-2) FPGA (Field Programmable Gate Array) platform is used for implementation and prototyping of the proposed hardware system, which totally uses 1897 LUTs (Look-Up Tables), 361 FFs (Flip-Flops) and 25 BRAMs (Block Random Access Memory) and consumes 2.016W at 100MHz. The experimental results show that the presented system can realize the FFT algorithm at any point by reconfiguring the parameters of software and expanding the capacity of the memory, and it is suitable for the embedded applications due to the small area and low power consumption.

模拟信息转换器(AIC)是模拟数字转换器的替代品,在频域稀疏信号处理中得到了广泛的应用.AIC通过将压缩感知理论从理想的数学计算模型直接映射到物理电路来实现稀疏傅里叶级数系数的测量,同时它引发了模型不匹配的固有问题.提出了一种基于系统状态空间模型系数矩阵的特征值映射的AIC设计方法,为如何从AIC计算模型出发设计电路参数提供了具体的方法.将此方法应用于无源开关电容采样电路,仿真结果表明:重构后的信噪比可达58.8 dB.

在产品生产线,复杂的装配任务往往需要操作人员拥有较为熟练的装配技术,并且需要大量的指导手册来获取装配指导信息,但是也无法完全避免出现装配错误,大大影响了装配效率.人工智能与图像识别在近几年得到了快速的发展与应用,并且开始逐渐应用于产品生产线,辅助操作人员进行装配操作,提高了装配效率、降低了装配错误率.文章基于图像识别技术,提出了一种利用摄像头,在装配工程中辅助操作人员协同完成装配,并精确定位装配区域,实现了装配区域识别、装配定位以及操作引导,在产品生产线上极具应用意义.

现有便携式心电采集系统需要低功耗高分辨率的模拟数字转换模块,虽然基于脉冲宽度调制的模拟信息转换器(AIC)可以有效降低系统的采样速率,但是该系统量化部分的转化时钟与量化精度成正比,因此存在功耗过高的问题.依据心电信号的能量不均衡特性,提出一种基于功率熵的精度可调时间-数字转换模块(TDC)设计方法.以能量最大化作为设计准则的基本思想,通过分析ECG信号的功率谱熵,确定系统观测向量所需的最小量化精度,实现AIC时间编码系统的优化设计.测试结果表明,该设计方法能够在压缩比为4,重构信噪比为38.91 dB,重构精度为0.36％的情况下,在采样心电信号的同时减少了 80％的TDC内部时钟动态翻转,从而有效降低功耗.