Too high power density has become critical problem during parallel multicast test of 3D chips.It could result in partial overheating and hotspots,so we propose a thermal-aware parallel testing method.Firstly,we analyse hotspots caused by parallel test in 3D chips.Then,the algorithms are presented to avoid the hotspots during the generation of test access paths for each kind of identical cores.Experiment results show that the temperatures on chip can be controlled and the hotspots can be eliminated efficiently.Furthermore,testing time can be reduced.

As CMOS device dimensions enter the nanometer era,test power has become much higher than the power produced in the circuit's functional mode,so test power is going to have a very important impact on VLSI design,and it has already been a hot topic in the research and industry areas.In this paper,some concepts of low-power testing are introduced,and leakage power and dynamic power are explained respectively.Some primary low-power techniques are described,and the transformation of the research focus and the trend of technical development are also discussed.

Using numerical simulation finite-element method,the vertical supporting capacity of large diameter predrilled cast-in-place pile is calculated.The influences of different thickness of bottom settlings are analyzed under pile and mud cakes around pile on the ultimate supporting capacity of single pile.The importance of controlling the thickness of bottom settlings and mud cake is discussed.Some particular measures were put forward as well.