This work presents a strain-gradient-driven synthetic antiferromagnetic (SAF) skyrmion neuron that implements leaky-integrate-fire (LIF) functionality through voltage-controlled magnetoelastic actuation. The proposed device comprises a SAF nanotrack elastically coupled to a piezoelectric PZT-5 H thin film, where the application of small voltages establishes programmable compressive or tensile strain gradients to drive skyrmion motion. Micromagnetic simulations demonstrate that the SAF configuration effectively suppresses the skyrmion Hall effect, ensuring rectilinear propagation and enabling a precise linear mapping between strain-gradient amplitude and skyrmion velocity. Building on these drift characteristics, a velocity-affine LIF model is formulated, in which integration ( Kint) and leakage ( Vleak) coefficients are quantitatively extracted from displacement-time trajectories and shown to scale linearly with the applied gradient. The derived neuron model is integrated into the SpikingJelly framework and evaluated within a 784-128-10 spiking neural network trained on the MNIST dataset. Network-level simulations reveal that the skyrmion-based neuron achieves training and inference accuracies exceeding 97%, matching the performance of standard LIF models while exhibiting reduced trial-to-trial variance. To assess hardware-level programmability and design robustness, a two-dimensional parameter sweep across the ( Kint,Vleak) space is performed. The resulting analysis identifies a broad operational region where inference accuracy remains robust, coinciding with a highly energy-efficient regime of approximately 0.5-1.0 pJ per spike. These results establish a skyrmion neuron architecture that is physically interpretable, energy-efficient, and tunably programmable, bridging nanoscale strain engineering with reliable system-level neuromorphic computation.

Silicon quantum dots (QDs) are essential physical carriers of quantum bits (qubits) in quantum computing. However, their extremely small size renders them highly sensitive to both the fabrication process and surrounding environment. Accuracy and stability must be carefully considered. In this study, we propose a double gate QD device model based on silicon metal-oxide-semiconductor (Si-MOS) for the generation of spin qubits. Using a Technology Computer Aided Design (TCAD) simulation, we investigated the impact of device dimensions, including oxide layer thickness, channel length, and spacer length, on the QD structure. Additionally, we examined the effects of the temperature and interface trap concentration on QD formation. An equivalent circuit model was employed to assess the charging energy (Ec) of QDs. Our results demonstrate that by appropriately adjusting these parameters, it is possible to achieve a QD structure with a wide level spacing and small size capable of accommodating as few as four electrons. Furthermore, we calculated an Ec of 33 meV for the QDs.

Vertically Stacked Nanosheet TFET (VNS-TFET) can break the subthreshold swing limit of MOSFETs and achieve higher layout efficiency. Due to the scaled-down device size, VNS-TEFT becomes vulnerable to process variability during fabrication. In this paper, the statistical impedance field method (sIFM) is used to investigate the effects of process variability, such as random doping fluctuations (RDF), work function variation (WFV), and oxide thickness variation (OTV), on VNS-TEFT. The standard deviation of the threshold voltage ( σ V t h ) is used to measure the effects of doping concentration, gate metal grain-related parameters and device parameters on the device process variability. The TCAD simulation results show that choosing an appropriate doping concentration for the source region can effectively reduce the effects of RDF. As the average grain size increases, the effect on WFV and OTV increases, but RDF has no effect. In addition, using a physical gate oxide with higher- κ in the VNS-TFET can effectively suppress WFV. Finally, it can be seen that the RDF is most sensitive to the size variation of the VNS-TFET.

In this paper, a vertically stacked nanosheet gate-all-around field-effect transistor (GAA-NSFET) as a label-free biosensor has been proposed and investigated. The influences of different biomolecules on the biosensor's electrical properties are analyzed, and the proposed biosensor exhibits good sensitivity for both neutral and charged biomolecules. Furthermore, a deep sensitivity analysis is performed to evaluate the sensing ability of biosensors with different channel structures. The sensitivity variation of biosensors is analyzed in terms of subthreshold swing (SS), threshold voltage (V-th), and current switching ratio (I-on/I-off). The results show that GAA-NSFET-based biosensor obtains the best sensitivity compared with other biosensors (including nanowire FET-based biosensor and vertically stacked nanowire FET-based biosensor) due to its larger channel width and multi-channels. Also, the influences of filling position on sensitivity are analyzed in various cases for the proposed biosensor. Its sensitivity depends on the filling amounts of biomolecules instead of the filling position. Finally, a status map is presented, which plots the sensitivity of some important works in biosensing application along with the sensitivity of the proposed biosensor, and GAA-NSFET-based biosensor is more sensitive compared with those works in terms of I-on = I-off sensitivity.

AES algorithm has a large amount of data migration between storage side and computing side. Especially on mobile devices, where the data migration demand is expensive, however, the existing Von Neumann architecture cannot support such demand due to the separation of storage and computation. Memristor, a new device, which integrates storage and computing together, is expected to solve the problem with low power and short delay of AES. The XOR logic operation plays centric rule in AES for carry addition and data encryption. However, the current researches on the logic operation of memristors only stays at basic logic (AND, OR, NOT) level, and the XOR logic operations constructed by these basic logics generally have problems such as too large area, long calculation sequence and complicated control. Therefore, this paper provides a new way to design energy efficient XOR logic and uses it to implement adder and AES encryption algorithm. The results show that the XOR logic method in this paper uses the least number of memristors and the shortest calculation sequence length comparing with the two popular baselines. The XOR logic based on memristor effectively decreases the power consumption and delay by at most 99% and 50% respectively.

In this paper, an analytical model for negative capacitance double gate field effect transistor (NC-DG-FET) is proposed. This model includes interface traps and temperature effects, which are ignored in previous investigations. In addition, the impacts of the ferroelectric thickness tFE, the interface trap density Dit and temperature T on the device performance are comprehensively discussed. The results indicate that, the minimum subthreshold swing is about 14 mV/decade with tFE = 75 nm, Dit = 5 × 1010 cm− 2/eV, T = 300 K. As Dit increases, the flat band voltage is decreased, which results in a gain peaking at a lower gate voltage, and a steeper subthreshold slope. When the temperature is raised from 300 K to 380 K, the NC effect is gradually weakened, resulting in a decrease in gain, and a smoothing of the subthreshold slope. We have verified our model by comparing it with experimental data and numerical simulation.

A new T-shaped tunnel field-effect transistor（TTFET） with gate dielectric spacer（GDS） structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling（BTBT） rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap（GDO） structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

L-shaped tunneling field-effect transistor (LTFET) has larger tunnel area than planar TFET, which leads to enhanced on-current ION. However, LTFET suffers from severe ambipolar behavior, which needs to be further optimized for low power and high-frequency applications. In this paper, both hetero-gate-dielectric (HGD) and lightly doped drain (LDD) structures are introduced into LTFET for suppression of ambipolarity and improvement of analog/RF performance of LTFET. Current-voltage characteristics, the variation of energy band diagrams, distribution of band-to-band tunneling (BTBT) generation and distribution of electric field are analyzed for our proposed HGD-LDD-LTFET. In addition, the effect of LDD on the ambipolar behavior of LTFET is investigated, the length and doping concentration of LDD is also optimized for better suppression of ambipolar current. Finally, analog/RF performance of HGD-LDD-LTFET are studied in terms of gate-source capacitance, gate-drain capacitance, cut-off frequency, and gain bandwidth production. TCAD simulation results show that HGD-LDD-LTFET not only drastically suppresses ambipolar current but also improves analog/RF performance compared with conventional LTFET.

In the present work, a nonplanar inverted π-shaped Si/Ge tunneling field effect transistor (πTFET) structure is proposed. The channel in πTFET is shaped as inverted π, and the hetero-gate-dielectric structure is used in this device (high-k over the source region, while low-k over the drain region) for . results show that πTFET effectively suppresses the ambipolar conduction, and simultaneously holds high ON-current.

针对计算机本科专业数字逻辑设计课程教学中面临的教学与实践内容相脱节、与后续相关课程不能有效衔接等状况,探讨面向计算机专业的数字逻辑课程架构,包括理论课教学内容和实验内容,重点分析教学过程中的重点和难点,特别是复杂数字系统设计中涉及的寄存器传输级模型、有限状态机控制等.

In order to analyze the performance of surrounding-gate Nanowire (SG-NW) junctionless (JL) FET under various temperatures, this paper introduces the incomplete ionization to modify the original model and presents a new precise model considering temperature effect. By solving surface potential based model, the electronic characteristics are compared with the results of the numerical simulation from three-dimensional device simulation software ISE TCAD.

Tip-enhanced Raman scattering (TERS) spectroscopy is a technique that employs near-field enhancement from a metallic nanotip to obtain Raman spectra with spatial resolution surpassing the diffraction limit. It is a useful nondestructive way to investigate the nanoscaled semiconductor films. In this paper, TERS technique is used to study the structural and functional properties of nitrogen doped 4H-SiC films. From the same TERS first-order Raman spectra obtained at several locations in 4H-SiC, we were able to reveal a good and uniform crystalline properties in nitrogen doped 4H-SiC. The spectra from tip-on experiments are nearly consistent with that from tip-off experiments. However, by the true near-field component obtained by subtracted tip-off experiment spectra from tip-on experiment spectra, we can see that not all Raman modes have the tip-enhanced effect. In TERS first-order spectra, E-2(TO), A1(LO) and E1(TO) modes were enhanced and confined; in TERS electronic Raman scattering from nitrogen in 4H-SiC, Nc and Nd modes were enhanced; in second-order Raman spectra, the overtone modes b, c, d and e were enhanced. But the reason of enhanced effect of these modes is not very clear yet.

With the exact solution of the 2-D Poisson's equation in cylindrical coordinates, analytical subthreshold behavior models for junctionless cylindrical surrounding-gate (JLCSG) MOSFETs are developed. Using these analytical models, subthreshold characteristics of JLCSG MOSFETs are investigated in terms of channel electrostatic potential distribution, subthreshold current, and subthreshold slope (SS). It is shown that the electrostatic potential distribution, subthreshold current, and SS predicted by the analytical models are in close agreement with 3-D numerical simulation results without the need of any fitting parameters. These analytical models not only provide useful physical insight into the subthreshold behaviors, but also offer basic design guideline for the nanoscale JLCSG MOSFETs.

SUMMARYInterface trap is directly related to the electrical characteristics and reliability of the transistor, and it is an important factor affecting the performance of the device. This paper presents an analytic surface‐potential‐based model for cylindrical silicon nanowire junctionless field‐effect transistors (Si‐NW JLFET) including interface traps. In this paper, the proposed model is applicable to all Si‐NW JLFET working region including different interface trap charges with several nanowire radii and doping concentrations. Simulation results show that interface trap charges present two properties (positive or negative) depending on the different positions of the Fermi level in band gap, which have a significantly influence on the surface potential to cause junctionless transistor subthreshold degradation and flatband shifting. In addition, appropriate device parameters can effectively reduce the impact to the characteristic of the device made by the interface trap without degrading the performance of device. Copyright © 2014 John Wiley & Sons, Ltd.

The Raman spectra of 4H-SiC with hexagonal defect have been investigated as a function of the excitation wavelength. As the excitation wavelength increases, the excitation wavelength dependence of Raman spectrum of hexagonal defect is very different from that of the free defect zone in 4H-SiC. Four electronic Raman scattering peaks are seen to be significantly enhanced with longer wavelength excitation. In hexagonal defect, the optical modes (E-2(TO), E-1(TO) and A(1)(LO)) and the second-order Raman spectrum are broadened and redshifted as the excitation wavelength increased. But the positions of these bands obtained from the free defect zone do not change within our experimental error. Structure defects are regarded as the origin of those abnormal phenomena in hexagonal defect, and the structure ordering of hexagonal defect may have some similarity with SiC monofilaments.

SUMMARYOn the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.

After analyzing the multivariate Cpm method（Chan et al.1991）,this paper presents a spatial multivariate process capability index（PCI） method,which can solve a multivariate off-centered case and may provide references for assuring and improving process quality level while achieving an overall evaluation of process quality. Examples for calculating multivariate PCI are given and the experimental results show that the systematic method presented is effective and actual.

In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

A continuous and analytic channel potential model for lightly doped gate-all-around (GAA) 6H-SiC nanowire (NW) FETs is developed incorporating the influence of incomplete dopant ionization. By solving the 1D Poisson's equation, and using Lambert-W function, the channel potential and the inversion charge are adequately described from the sub-treshold to the strong inversion.

A novel asymmetric HALO-doped surrounding-gate MOSFET with gate overlapped lightly-doped drain is presented. The performance of the new structure is studied by developing physics-based analytical models for surface potential, threshold voltage, and subthreshold current. It is found that the new structure can effectively suppress the short-channel effects and the hot-carrier effects, and simultaneously reduce the off-state current. It is also revealed that subthreshold current is a slight function of doping concentration of overlapped region, while work-function of gate electrode has a strong influence on subthreshold current. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.