Aiming at the "reboot stuck after power-off following OS crash" issue in ARM v8-based Information and Communications Technology (ICT) Innovation devices (e.g., Phytium FT2000/4, Phytium D2000), this study reveals that the core mechanism is the corruption of the UEFI BIOS Non-Volatile (NV) Variable Region, caused by interrupted log writing of the Linux kernel’s Pstore Module. A three-layer protection scheme ("Source Control – Process Protection – Post-Failure Repair") is proposed: source control prevents corruption by redirecting Pstore logs to SSDs; process protection ensures boot availability via the BIOS CRC verification and dual-copy mechanism; post-failure repair enables rapid maintenance through remote operations based on the Phytium E2000S BMC. Experimental verification shows that the scheme reduces the NV Variable Region corruption rate from 5.5% to an undetected level (≤ 0.1%), improves the boot success rate to 100%, and enhances repair efficiency by 12 times compared with the traditional "offline BIOS chip burning" method. Without modifying ARM hardware, the scheme meets the reliability requirements of financial transaction systems and e-government scenarios, filling the research gap in NV Variable Region protection for UEFI BIOS on ARM platforms.

Direct Memory Access (DMA) enhances data transmission efficiency in embedded firmware but introduces significant challenges to dynamic analysis due to its CPU-bypassing and asynchronous characteristics. Existing DMA-aware analysis approaches rely on Hardware Abstraction Layer (HAL) source code availability or heuristic inference, suffering from limited adaptability, insufficient precision, and high performance overhead. This paper presents DMA-Enhanced Firmware Analysis (DEFA), a dedicated framework for dynamic analysis of DMA-enabled ARM Cortex-M firmware. DEFA integrates dual-mode DMA channel detection combining HAL function interception and register-level monitoring, and achieves automatic MCU model identification for symbol-free firmware by fusing static binary features with dynamic execution traces. A stateful DMA Transfer Descriptor Manager (TDM) is designed to track the complete lifecycle ofDMAtransfers, complemented by a lightweight memory access hooking mechanism for seamless integration with mainstream fuzzers and emulators. Comprehensive evaluations on 145 cross-vendor MCU firmware samples demonstrate that DEFA achieves 90.3% MCU recognition accuracy (micro-average; 95.2% macro-average) with merely 1.4% average runtime overhead for DMA analysis. Compared with the state-of-the-art tool DICE, DEFA improves fuzzing execution efficiency by 35.2% while detecting an equivalent number of DMA-related memory safety violations. DEFA effectively overcomes critical limitations of existing DMA firmware analysis tools and provides a practical solution for security analysis of IoT and industrial embedded systems.

Offline data leakage from internal SATA storage remains a critical security challenge in modern trusted computing systems, as existing TPM/TCM-based trusted platforms rely on passive integrity measurement and fail to protect data when SATA SSDs are physically removed. This paper proposes a novel secure computer architecture integrating a Trusted Platform Control Module (TPCM) as an active root of trust with a hardware-accelerated SATA encryption/decryption engine. The TPCM acts as the core for key lifecycle management and enforces bilateral authentication with the SATA encryption chip to ensure exclusive disk-platform binding, while the ASIC-based encryption engine implements real-time AES-XTS-512 encryption/decryption for all SATA bus data to mitigate offline data leakage risks. A prototype built on the Phytium FT2000/4 processor platform achieves sequential read/write throughputs of 513.6 MB/s and 469.5 MB/s, with a maximum encryption overhead of 8.2% compared to non-encrypted systems—consistent with industrial real-time requirements. Additionally, the design initiates logical or physical data destruction upon authentication failure, with all key distribution processes managed securely by the TPCM. Within the evaluated prototype, firmware tampering was detected in all injected samples and no plaintext key leakage was captured under penetration tests; these security claims are bounded to the tested scope. This work addresses the critical gap between trusted computing and storage security, providing a practical solution for embedded industrial systems requiring robust offline data protection.

In embedded system development, firmware testing for microcontrollers faces challenges such as high hardware dependency costs and incomplete test scenario coverage. This paper proposes an I2C controller and peripheral emulation method based on the Unicorn emulator and Socket communication, which achieves full-scene emulation of the STM32 microcontroller's I2C interface through a three-layer architecture (instruction set emulation layer, master controller emulation layer, and slave device emulation layer). The scheme adopts a Finite State Machine (FSM) to manage communication states and custom protocols for inter-module data interaction, thereby enabling hardware-free dynamic firmware emulation. Experiments show that the model accurately simulates five I2C operation modes (e.g., byte write, sequential read), with an average I2C interaction delay of $45 \mu \mathrm{s}$ and 1-hour stable concurrent emulation of multiple peripherals in the STM32F407 health management firmware. It provides an efficient hardware-free solution for embedded firmware testing.

This paper focuses on the vulnerability of UEFI Firmware runtime services in ARM-based servers. In typical server hardware designs, the main processor and out-of-band management system (BMC, Baseboard Management Controller) share a Real-Time Clock (RTC) chip, where the BMC controls access priority through GPIO-based time-division multiplexing (TDM). The study reveals that a customized firmware has design flaws in handling RTC access conflicts, resulting in illegal address access when the operating system (OS) invokes timerelated services, thereby triggering system crashes. Through fault localization, mechanism analysis, and experimental verification, this paper uncovers the interactive vulnerabilities between hardware access conflicts and software service implementations, and proposes solutions including virtual address translation and retry mechanisms, offering valuable insights for reliability design in similar architectures.

Featuring with characteristics of convolutional neural network (CNN) and recurrent neural network (RNN), hybrid neural network (H-NN) has been widely applied within the field of remote sensing. In order to satisfy de mands of on-orbit processing that requires high throughput with restriction on power consumption, designing specific heterogeneous array processor therefore becomes one of the most effective ways fulfilling various tasks engaged in the above field. In this paper, a heterogeneous array architecture is proposed to support the hybrid neural network, based on the characteristics of various computation types in between different neural network module types and of dynamic computation burden among different layers. Firstly, a heterogeneous array structure consisting of different PE, PPE, RPE and LPE units is proposed, enabling strong flexibility and high throughput. Four types of operation units are used for operations of MAC, ReLU, pooling and nonlinear lookup-table. Secondly, a multi-level on-chip memory structure and access strategy supporting different access modes are proposed to reduce the bandwidth requirements of off-chip data access and to improve the computation efficiency. Thirdly, a management strategy of heterogeneous computing array is designed, which combines pipelining and parallel processing to support efficient mapping of different types of hybrid neural networks. The hybrid neural network processor based on 65 nm CMOS technique has a peak throughput of up to 1.96 TOPS. The implementation on models of AlexNet, LRCN, VGG19-LSTM and CLDNN can achieve the throughput of 1.92 TOPS, 1.89 TOPS, 1.93 TOPS and 1.84 TOPS, respectively. Compared with the similar neural network processor that is based on the same technology, the throughput of AlexNet model is increased by 76.4%. The peak power consumption of a single processor core is 824mW, to which the power consumption restriction of on-orbit AI platform is satisfied.

In recent years, there has been rapid development in machine learning for solving artificial intelligence tasks in various fields, including translation, speech, and image processing. These AI tasks are often interconnected rather than independent. One specific type of relationship is known as structural duality, which exists between multiple pairs of artificial intelligence tasks. The concept of dual learning has gained significant attention in the fields of machine learning, computer vision, and natural language processing. Dual learning involves using primitive tasks (mapping from domains X to Y) and dual tasks (mapping from domains Y to X) to enhance the performance of both tasks. In this study, we propose a general framework called Bi-Dual Inference by combining the principles of dual inference and dual learning. Our framework generates multiple dual models and a primal model by utilizing two dual tasks: sentiment analysis of input text and sentence generation of sentiment labels. We create these model pairs (primal model f, dual model g) by employing different initialization seeds and data access sequences. Each primal and dual model is considered as a distinct LSTM model. By reasoning about a single task with multiple similar models in the same direction, our framework achieves improved classification results. To validate the effectiveness of our proposed model, we conduct experiments on two datasets, namely NLPCC2013 and NLPCC2014. The results demonstrate that our model outperforms the optimal baseline model in terms of the F1 score, achieving an improvement of approximately 5%. Additionally, we provide parameter values for our proposed model, including model iteration analysis, α parameter analysis, λ parameter analysis, batch size analysis, training sentence length analysis, and hidden layer size setting. These experimental results further confirm the effectiveness of our proposed model.

The satellite-borne SAR image intelligent processing system needs to process on-orbit real-time imaging and various tasks of applications, for which reason designing a dedicated high-efficient single-chip multi-processor is of prioritized necessity that can simultaneously satisfy requirements of real-time and low power consumption. Aiming at on-chip data organization and memory access structure, two typical models of SAR(synthetic aperture radar) imaging CSA (chirp scaling) and neural network VGG-11 are analyzed, and then a collaborative computing model for the intelligent processing on remote sensing is extracted. A strip Tile data processing scheme and a dedicated multi-processing architecture is not only proposed, but a data organization and a caching strategy of Tile space synchronization splicing is also presented. In addition, the designed data caching structure among the processing units greatly reduces off-chip access memory bandwidth while supporting parallel pipeline execution of multi-task model. The chip adopts 28 nm CMOS technology featuring with merely 1.83 W of the overall power consumption, whose throughput and energy efficiency reaches 9.89TOPS and 5.4 TOPS/W, respectively. The present architecture can improve real-time performance of the on-orbit remote sensing intelligent processing platform while reducing the complexity of system designing, which is highly adaptive to differentiated expansions according to different models of algorithm.

Spaceborne SAR(synthetic aperture radar) imaging requires real-time processing of enormous amount of input data with limited power consumption. Designing advanced heterogeneous array processors is an effective way to meet the requirements of power constraints and real-time processing of application systems. To design an efficient SAR imaging processor, the on-chip data organization structure and access strategy are of critical importance. Taking the typical SAR imaging algorithm-chirp scaling algorithm-as the targeted algorithm, this paper analyzes the characteristics of each calculation stage engaged in the SAR imaging process, and extracts the data flow model of SAR imaging, and proposes a storage strategy of cross-region cross-placement and data sorting synchronization execution to ensure FFT/IFFT calculation pipelining parallel operation. The memory wall problem can be alleviated through on-chip multi-level data buffer structure, ensuring the sufficient data providing of the imaging calculation pipeline. Based on this memory organization and access strategy, the SAR imaging pipeline process that effectively supports FFT/IFFT and phase compensation operations is therefore optimized. The processor based on this storage strategy can realize the throughput of up to 115.2 GOPS, and the energy efficiency of up to 254 GOPS/W can be achieved by implementing 65 nm technology. Compared with conventional CPU+GPU acceleration solutions, the performance to power consumption ratio is increased by 63.4 times. The proposed architecture can not only improve the real-time performance, but also reduces the design complexity of the SAR imaging system, which facilitates excellent performance in tailoring and scalability, satisfying the practical needs of different SAR imaging platforms.

Hybrid neural network (H-NN) has been applied in field of remote sensing. To satisfy demands of on-orbit processing that requires high throughput and restriction on power consumption, designing heterogeneous array processor becomes an effective way fulfilling various tasks. A heterogeneous array architecture is proposed to support the hybrid neural network based on characteristics of various computation types among neural network module types and of dynamic computation burden among layers. Firstly, a heterogeneous array structure consisting of different types of PEs is designed, enabling strong flexibility and high throughput. Secondly, multi-level on-chip memory structure and access strategy supporting different access modes are proposed. Thirdly, management strategy for heterogeneous computing array is designed, which combines pipelining and parallel processing to support efficient mapping of diverse hybrid neural networks. The processor has a peak throughput of up to 1.96 TOPS. The implementation on models of AlexNet, LRCN, VGG19-LSTM and CLDNN can achieve the throughput of 1.92 TOPS, 1.89 TOPS, 1.93 TOPS and 1.84 TOPS, respectively. Compared with similar neural network processor that is based on same technology, the throughput of AlexNet model is increased by 76.4%. The peak power consumption of single processor is 824 mW, to which the power restriction of on-orbit AI platform is satisfied.

The expansion and improvement of synthetic aperture radar (SAR) technology have greatly enhanced its practicality. SAR imaging requires real-time processing with limited power consumption for large input images. Designing a specific heterogeneous array processor is an effective approach to meet the power consumption constraints and real-time processing requirements of an application system. In this paper, taking a commonly used algorithm for SAR imaging—the chirp scaling algorithm (CSA)—as an example, the characteristics of each calculation stage in the SAR imaging process is analyzed, and the data flow model of SAR imaging is extracted. A heterogeneous array architecture for SAR imaging that effectively supports Fast Fourier Transformation/Inverse Fast Fourier Transform (FFT/IFFT) and phase compensation operations is proposed. First, a heterogeneous array architecture consisting of fixed-point PE units and floating-point FPE units, which are respectively proposed for the FFT/IFFT and phase compensation operations, increasing energy efficiency by 50% compared with the architecture using floating-point units. Second, data cross-placement and simultaneous access strategies are proposed to support the intra-block parallel processing of SAR block imaging, achieving up to 115.2 GOPS throughput. Third, a resource management strategy for heterogeneous computing arrays is designed, which supports the pipeline processing of FFT/IFFT and phase compensation operation, improving PE utilization by a factor of 1.82 and increasing energy efficiency by a factor of 1.5. Implemented in 65-nm technology, the experimental results show that the processor can achieve energy efficiency of up to 254 GOPS/W. The imaging fidelity and accuracy of the proposed processor were verified by evaluating the image quality of the actual scene.

设计了一种针对图像处理类应用程序的并行性分类的方法,并使用工具初步实现了对程序的分类.还研究了图像处理算法的并行性.通过对图像处理算法的主要特征进行分析,得出图像处理算法包含多种并行特征的结论,分别从图像处理程序的混合结构的模型,以及程序中的依赖关系和并行特征两方面进行了分析.结合对程序的分类方式,使用LLVM编译架构初步实现了自动对程序中的程序段进行识别其中的分类模式.

针对计算机本科专业数字逻辑设计课程教学中面临的教学与实践内容相脱节、与后续相关课程不能有效衔接等状况,探讨面向计算机专业的数字逻辑课程架构,包括理论课教学内容和实验内容,重点分析教学过程中的重点和难点,特别是复杂数字系统设计中涉及的寄存器传输级模型、有限状态机控制等.

Application Defect induced by GPU Aiming at SAR Imaging are studied. It is the first time the issue of application defect induced by GPU is addressed in SAR field. In GPU-based SAR imaging system, application defect induced by resources competition can significantly decrease the granularity of parallelism. To solve this problem, the GPU-based SAR imaging system with CUDA is firstly modeled. Secondly, conditions of parallel granularity loss rate by using CUDA are obtained based on time output feedback scheme. Thirdly, more importantly, find the difficulties and bottlenecks in the optimization of SAR imaging operation is proposed according to the measured conditions of parallel granularity loss rate. Finally, optimization bottleneck analysis through FFT function and linear matrix interpolation scheme, and numerical simulations are made to demonstrate the effectiveness of the proposed scheme.

With the decrease of the grain size, the leakage power of traditional on-chip SRAM-based Cache increases expo-nentially, which hinders the increase of capacity of Cache on chip. As SRAM’s write speed is faster and STT-RAM is non-volatile, high density and very low leakage power, this paper designs a hybrid instruction Cache with SRAM and STT-RAM. The experimental results show that, compared with the SRAM-based instruction Cache, the hybrid instruction Cache increases capacity and significantly improves the hit rate without increasing the area.

Generally, zip password recovery software uses CPUs to crack password, which can only try a few passwords per seconds, and it takes a long time to find out the correct password. This paper proposes a fast zip password recovery algo-rithm on GPU, the AES decryption and HMAC algorithm are optimized for GPU specially. This algorithm takes advan-tage of password verification value to reject many incorrect passwords. The algorithm uses macro to optimize the usage of GPU registers, the computing resources have been fully used. The experimental result shows that GPU can achieve 11.09 times speedup compared with the CPU.

With the growth of the depth and complexity of pipeline, it needs more and more effort to verify a pipeline. Closed-loop Feedback (CLF), a method which can verify complex pipeline, is proposed in this paper. In CLF, activities of pipeline are fed back to verification pattern generator, where it can be used to generate the following verification patterns dynamically and automatically. Compared with non-feedback by simulation, CLF can achieve the goal of verification much more quickly.

支持片上在线调试是嵌入式SoC设计目标之一;现有的片上调试系统多基于扫描链技术,SoC系统的功能设计和调试设计必须同步,这种紧耦合的设计方法移植性差、通用性弱,与SoC系统IP复用的理念不符;基于此,提出了一种基于片上标准总线的SoC在线调试方法,该方法引入调试主设备的概念,复用片上总线传输实时调试数据,实现了对SOC外围IP的在线调试,同时通过引入调试支持单元和调试处理模块实现了对处理器主设备的总线访问调试;该方法适用于以标准总线结构互联的SOC系统,具有适用性广、调试功能丰富、调试接口多样、调试效率高等优点;该方法在以SPARC处理器为处理核心、AMBA总线为互联的SoC系统中进行了实现和在线调试验证,实验表明满足SoC的调试需求。

Supporting the online debugging is one of the design goals of SoC. Usually the function unit and the debugging structure are tightly coupled, thus it is hard to reuse the debug structure in other systems. This paper presents an on-chip debug method for SoC bus architecture. The system reuses On Chip Bus(OCB) as the transmission path for debugging data and debugs the units in system in form of bus access through debug interface. To implement debugging of embedded processor, Debug Support Unit and Debug Handle Unit is designed. The method fits for mainstream SoCs. It includes various debug functions and few limitations of debug interface, which is also very efficient. SoC of AMBA architecture with debug architecture of this kind has been implemented, and the debug function has been verified. The experiment indicates that the design satisfies the demand of SoC debugging.

To protect the Intellectual Property of Integrated Circuit, We present a novel architecture which exploits and analyze error information produced by an embedded timing-fault execution unit in the data path of a microprocessor. As the timing of the fault execution circuit doesn't meet microprocessor global timing requirement intentionally, the computation result appears randomly error and will depend on manufacturing process environment ultimately. Because of the variations of the manufacturing process, the error information will vary between different chips and will not be easily predicted. The timing-fault execution unit is a kind of PUF (Physical Unclonable Function) essentially, it utilizes setup time violations of D-type Flip-flop to identify and encrypt microprocessor. We verify the idea in Diligent Genesys Xilinx FPGA board by implanting one 32-bit timing-fault adder in a processor RTL model. It demonstrated that the error information produced by the timing fault unit is unique and has better random distribution, also the method can be easily integrated into the microprocessor design flow and Complex Challenge-Response pairs can be generated and captured by online high-level instruction streams. We argue the proposed architecture is a more practical and hopeful way to identify processor chips.