A novel indolo[3,2-b]carbazole derivative containing B(Mes)2 groups, 5,11-dibutyl-2,8-bis(dimesitylboryl) indolo[3,2-b]carbazole (DBDMBICZ), was synthesized and structurally characterized by elemental analysis, NMR, MS. The thermal, electrochemical and photophysical properties of DBDMBICZ were characterized by thermogravimetric analysis, electrochemical methods, UV–vis absorption spectroscopy and fluorescence spectroscopy. DBDMBICZ exhibited high fluorescence quantum yields (Φmax=0.76) in solution and excellent thermal stability (Td=290°C, Tg=170°C) and electrochemical stability. The multi-layered OLEDs devices with the configuration of ITO/NPB/CBP/light-emitting layer/Bphen/LiF/Al are fabricated by using DBDMBICZ as light-emitting layer. The devices show the same pure blue emissions at different voltages and relative good electroluminescent performances. The results indicate that DBDMBICZ has potential applications as an excellent optoelectronic material in optical field.

Nanoparticles of a novel boron-based carbazole derivative have been reported. They exhibit efficient green fluorescence, aggregation induced ratiometric fluorescence change and green/blue fluorescent switching to sense VOCs.

To reduce interference of the shared LLC on a chip Multi-Processor(CMP) architecture,we propose a Replacement policy based Reusable Data Predicting mechanism(RRDP) to select possible reused data from replaced data according to the memory access frequency characteristics of application.When some data will be replaced in LLC Cache,we filter out predicted reusable data by checking their history reference information,and store them into a dedicated on-chip memory.Our simulation results show that the proposed mechanism increases the IPC of programs by 2.9% on average and reduces the harmful replacements by 22.69%,so it can effectively reduce Cache thrashing.

A novel A-π-D-π-D-π-A type compound, containing two benzothiazole rings as electron acceptors and two N-ethylcarbazole groups as electron donors, (E)-1,2-bis(3-(benzothiazol-2-yl)-9-ethylcarbazol-6-yl)ethene (BBECE), was synthesized and characterized by elemental analysis, NMR, MS and thermogravimetric analysis. Electrochemical property of compound BBECE was studied by cyclic voltammetry analysis. The absorption and emission spectra of BBECE was experimentally determined in several solvents and simultaneously computed using density functional theory (DFT) and time-dependent density functional theory (TDDFT). The calculated absorption and emission wavelengths are coincident with the measured data. The lowest-lying absorption spectra can be mainly attributed to intramolecular charge transfer (ICT), and the fluorescence spectra can be mainly described as originating from an excited state with intramolecular charge transfer (ICT) character. The molecular orbitals (HOMO and LUMO), the ionization potential (IP), the electron affinity (EA) and reorganization energy of compound BBECE were also investigated using density functional theory (DFT). The results show that compound BBECE exhibited excellent thermal stability and electrochemical stability as well as high fluorescence quantum yield, indicating its potential applications as an excellent optoelectronic material in optical fields.

A novel boron-containing π-conjugated compound has been synthesized by the introduction of electron-acceptors (dimesitylboron groups) at the 3,3'-positions of a carbazole dimer (electron-donor). The compound possesses excellent electrochemical properties and high fluorescence quantum yields. In addition, is a sensitive fluorescence sensor with remarkable colour changes and the results could be confirmed through theoretical calculations of the compounds and [(n)Bu(4)N](+)(2)[·(F)(2)](2-). Our studies indicate that could be used as an excellent optoelectronic material in OLED devices and a ratiometric fluorescent chemosensor.

Three novel indolo[3,2-b]carbazoles derivatives were successfully synthesized by condensation reaction and structurally characterized by elemental analysis, mass spectrometry and proton nuclear magnetic resonance spectroscopy methods, which belong to donor-π-acceptor systems comprising an indolo[3,2-b]carbazole group as an electron donor and two benzothiazole rings as electron acceptors. The thermal, electrochemical and photophysical properties of the compounds were characterized by thermogravimetric analysis combined with electrochemistry, UV–vis absorption spectroscopy and fluorescence spectroscopy. On the other hand, the geometries, molecular orbitals, charge-injection and transport properties were determined by quantum chemical calculations. The results show that the compounds synthesized exhibit good thermal stability and high fluorescence quantum yields, indicating the potential application as optoelectronic materials.

A 32-bit embedded RISC processor is presented which is compatible with the PowerPC architecture. To make a balance between its area, power, performance and real-time response, a smart micro-architecture is proposed with the distinguishing feature of dual-issue and dual-pipeline. The key point of the architecture is that the instruction dispatching engine dynamically scans the data dependences between two consecutive instructions in the instruction queue and decides whether or not to perform dual-issue action in advance. The intelligent engine parses the mutual-dependence relationships of the two instructions at the head of the queue. If the destinations of the first instruction are not the sources of the second adjacent instruction, the two instructions are allowed to be dispatched in parallel; otherwise they must be dispatched in sequence. Two independent pipelines can execute the two instructions and the dedicated data-forward buses are adopted to resolve the dependences between the multi-instructions. We use the HDL to build the model to evaluate the micro-architecture for accelerating the arithmetic instructions, and we use the Mibench to evaluate the proposed architecture. It is demonstrated that the average IPC of the smart architecture reaches 1.5. Compared to the single issue architecture, it can effectively improve the performance; and compared to the OOO(Out-of-Order) architecture it can reduce the area, the power and the verification complexity. During the experiment, we also find that the memory latency is the performance bottleneck. Finally, we give a brief discussion about the test circuit and the physical design. The processor is fabricated by SMIC 1P6M 180 nm CMOS technology, the die area is 5.9 × 6.7m 2 and the core frequency is 266 MHz..

Translation Look-Aside Buffer(TLB) is a dedicated hardware component that the Memory Management Unit(MMU) utilizes to improve page address tanslation speed.However,some researchers indicate that working TLBs may occupy as much as 17% of a processor's total power consumption.The objective of this paper is to effectively reduce the TLB on-chip power consumption by looking into the program behavior in respect of page access traits.With careful analysis of the memory access patterns of SPEC CPU benchmarks,we demonstrated that the Page Interval which non-sequential page accesses heavily exhibit can be used to largely reduce the power of TLBs.Based on this observation,we proposed a novel low-power TLB design methodology.Experimental results show that using our design the on-chip power consumption can be further saved.

Aggressive prefetching may cause much inter-core interference and lead to large performance in shared memory CMP systems. The paper aims at improving system performance and making prefetching effective. We study prefetching-caused inter-core interference of CMP system and propose a Global Prefetcher Aggressiveness Control Scheme (GPACS) to reduce useless and aggressive prefetches. It controls the aggressiveness of multiple hardware prefetchers of different cores in CMP using a global control mechanism. The key idea of the scheme is taking into account both shared last level cache and memory queue prefetch-caused inter-core interference for determining the aggressiveness of each core's prefetcher. Our evaluations show that GPACS significantly improves the performance of prefetching with a low-hardware cost and makes it effective in multi-core environments.

Based on hydraulic flow analysis of forebay and field tests before rehabilitation,the turbulent flow pattern in Tianshan first level pumping station was found,which caused intensive vibration and intermittent vibration of pump units.Then the technical measure of discontinuous trajectory bucket energy dissipation and sediment prevention(DTBED & SPTM),which involves discontinuous bottom baffle sills,discontinuous trajectory bucket piers and two pressure plates,was presented.The experimental results after rehabilitation show that,with the application of the technical measure,flow patterns of forebay and sump,as well as the pump intake condition are significantly improved,velocity distribution of forebay middle section is uniform and turbulent energy is decreased obviously.The flow rate of single pump,the pump efficiency and device efficiency of pumping station are averagely increased 0.14 m3/s,4.99% and 3.88%,respectively.The intermittent vibration of pump body is eliminated,and the vibration standard of pump bell mouth intake decreases from intensity stage 4.5 to intensity stage 1.8.The sediment deposition of forebay and sump is slowed down,and the sediment removing time is extended from 800 hours before rehabilitation to 1 300 hours after rehabilitation,which proves effective in sediment prevention.The DTBED & SPTM offers a simple yet effective approach to technical rehabilitation of pumping station technological rehabilitation on rivers with high sediment content.

At the Tianshan first-grade pumping station,water level of the forebay and suction sump is controlled by a sluice at the forebay inlet.To improve flow patterns formed by the jet under the sluice,the RANS equations and a standard k-e turbulence model are used to simulate the flow and to study different schemes.Simulation results show that the most effective scheme is the one combining three engineering measures,non-continuous bottom sills,non-continuous trajectory sills and pressurized water plate.In this scheme,the overall flow in the forebay and suction sump is improved with smaller velocities near the bottom and around the pump inlet.Sediment accumulations in the forebay and behind the bottom sills and trajectory sills are avoided or decreased.Field test showed that since the proposed schemes were adopted,pumping station vibrations have been reduced obviously,operating efficiency of the pump increased,and sediment accumulation decreased.These results provide important data for renovation of foreby and suction sump of the pumping stations on Yellow River.

Two novel pyrazoline derivatives, named 2,8-bis(1,3-diphenyl-pyrazoline-5-yl)dibenzofuran (A) and 2,8-bis(1-(4-bromophenyl)-3-phenyl-pyrazoline-5-yl)dibenzofuran (B), were synthesized and characterized by elemental analysis, NMR, MS and thermogravimetric analysis. The absorption and emission spectra of them were determined by experimental methods in different polar solvents and were computed using the density functional theory (DFT) and the time-dependent density functional theory (TDDFT) at the same time. The calculated absorption and emission wavelengths are in good agreement with the experimental data. The fluorescence quantum yields and fluorescence lifetimes of them in different polar solvents were studied by means of steady state and time resolved fluorescence. The calculated reorganization energy for hole and electron indicates that the two compounds are in favor of hole transport than electron transport. The results show the two compounds present high fluorescence quantum yields and excellent thermal stability. It makes them of great interest as novel fluorescent probes and optoelectronic materials.

According to the jet feature under the sluice that formed by the water level difference in Tianshan first-stage pumping station, the efforts of fluid meliorating were put forward. The RANS equation and standard k-ε turbulence model were used to simulate the flow state, and the influence of sediment on the water flow was not taken into consideration during the simulating process. Due to the attempts of adopting discontinuous bottom sills, discontinuous trajectory sills and pressurized water board, the results show that the jet length is shorten significantly, the surface backflow disappears, the cross-section velocity distribution tends to uniform, and the velocity at the bottom of the forebay and suction bay and near the pump inlet decreases significantly. The field investigations show that the modifications adopted increase the device efficiency by 1.82% and 5.96% respectively. The vibration amplitude decreases 21 μm and 52 μm, and the sediment accumulation almost disappears in both operating conditions.

Temperature measurements have been carried out on a 17.5 ton experimental steel casting to determine the thermophysical properties of sand mold for heavy steel castings. The determined thermophysical data are used in the solidification simulation to predict shrinkage porosity in a 300 ton lower cross-head casting of rapid forging press. Results demonstrate that the thermal conductivity of sand mold is the minimum at 400 ℃, while the increase of the specific heat with temperature slows down after 600 ℃. Furthermore, the optimization of chill and padding design leads to desirable feeding which eliminates the shrinkage cavity and porosity of the lower cross-head casting.

Low-power design is quite necessary for the modern power-sensitive embedded systems. Translation Look-aside Buffers (TLBs) can take up significant on-chip energy while translating page addresses. In this paper, we study the memory access behavior of applications drawn from SPEC benchmark suits. In such study, we define a parameter, page interval, to direct our research on saving the power dissipation of dTLB. After that, we present an optimized low-power design for dTLB by introducing an Access Recording Buffer (ARB). The ARB specifically records the high-order bits of the recently-used logical address and that of the corresponding physical address. To decide the optimal configuration of the ARB, we further study different depths and replacement policies to observe their effects on system performance and energy consumption. By running applications drawn from SPEC benchmark suits, the experiment shows most page address translation can be done in the ARB, thus significantly reducing the need to look up the dTLB. Our experiments show that using the ARB can yield an average on-chip energy saving of 30% for dTLB.

Memory system of chip multi-threaded processors (CMT) suffers greater than ever before because of memory latencies brought by overloaded memory accessing requests. Data prefetching using helper threads has been proved to be an effective approach to tolerate memory latencies by past researches. However, as the sum total of threads increase, simultaneously occupying available idle thread context in each core, there exist the possibility in which resource contention happen frequently among helper threads and main threads. This paper proposes to devise the helper threaded prefetching utilizing independent navigating core, where helper thread runs, for each processor core. With this method, helper thread can be freed from resource limitation and take advantage of helper threaded prefetching strategy, consequently promoting the holistic performance of chip multi-threaded processors. Experimenting results demonstrate that by using navigating core helper threaded prefetching can well improve instruction per cycle and remarkably reduce miss ratio of delinquent loads compared with a traditional helper threaded prefetching strategy.

Simultaneous multithreading(SMT)is a technique that permits multiple independent threads to issue multiple instructions each cycle to a superscalar processor’s functional units.This technique can exploit both instruction -level and thread -level parallelism to improve the performance.Based on a 32-bit superscalar processor (Longtium R2),present the architecture equipped with the simultaneous multithreading technique.The data,gained from simulation,show that the throughput increment can be achieved without extensively changing the original structures or increasing the additional execution units of a superscalar processor.After using the SMT technique,the processor can achieves up to 50% performance improvement,although influenced by some restrictions.

With the advent of chip multiprocessor (CMP) architecture, programmer must tune the program to the architecture in order to fully utilize the hardware resource. How to parallel program multimedia application in the CMP is a big obstacle. In this paper, we introduce the potential parallelism in the multimedia application and the multi-grain parallelism architecture in the CMP; also we make a systematic analysis on how to exploit multi-grain parallelism to accelerate the multimedia application computing. A method based on the multigrain parallelism in the CMP is proposed to instruct the programmer to effectively layout the multimedia-related program. The method exploits the parallelisms from data-level, instruction-level, thread-level, and memory-transfer level. The Experimental results indicate that the method is practical and effective.

The mould filling and solidification process of the casting of 80MN rapid forging press upper beam were simulated with MAGMA.The effect of gating system design,setting of feeder,position and the size of surface chill on the solidification defect was analyzed.Basing on these results,we have predicted the position of shrinkage and porosity in the casting,and have successfully optimized the casting technique of rapid forging press upper beam.