Function secret sharing (FSS) has become a core primitive in privacy-preserving computation. However, each FSS invocation requires a fresh pair of function keys generated by a trusted dealer , expands the system's trust boundary and hinders practical deployment. Existing dealerless protocols eliminate this dependency, but incur substantial communication and a number of interaction rounds that grows linearly with the input bit-width, making key generation a major bottleneck. This paper present KORD, a protocol–hardware co-design that dramatically reduces the cost of dealerless FSS key generation. At its core is a pair of special-purpose chips that establish a common root of trust through mutual attestation and, within it, reconstruct FSS keys—eliminating the need for a dealer. This root of trust further forms a security boundary within which KORD restructures the generation protocol, collapsing the interaction of prior dealerless protocols into a single round, independent of GGM depth. A cross-key scheduling scheme then interleaves independent GGM-tree traversals, sustaining high computational throughput. KORD reduces per-key-generation communication by 7,633–70,274× over the state-of-the-art distributed FSS protocol across a comprehensive suite of FSS building blocks. Post-route analysis projects 12.75 million 32-bit DPF keys per second at 204 MHz using 21.5K LUTs, with 99.8

As integrated circuits are increasingly deployed in security-critical applications, assessing the risk of information leakage introduced during the design phase has become a key challenge. Logic-level structures may inadvertently enable sensitive data to propagate to externally observable points, posing serious security risks. Although anomaly-based techniques such as taint tracking and machine learning have been developed to detect or mitigate leakage threats, the absence of a unified and quantitative metric for evaluating leakage risk remains a major limitation. Without such a metric, existing methods can neither effectively identify real threats nor compare the effectiveness of protection strategies in a principled manner, leading to limited reliability and comparability in hardware security analysis.To overcome these challenges, we propose GLRA, a graph-based methodology for leakage risk assessment via minimal transmission cost path analysis. Departing from the traditional “path existence” criterion used in anomaly label-based taint tracking, GLRA quantifies leakage risk by evaluating the difficulty of information propagation. A central premise of GLRA is that the transmission cost—defined as the effort required to propagate signals from sensitive sources to observable outputs—is inversely correlated with leakage likelihood: lower costs imply higher risks. Accordingly, we define controllability-based transmission cost metrics for basic logical units such as AND, OR, NOT, and DFF, which quantify the propagation effort imposed by each logic unit. By modeling the circuit as an edge-weighted graph where edges are annotated with the aforementioned transmission cost values, GLRA identifies the minimal path from sensitive sources to potential leakage points. In addition, to accurately quantify the risk of leakage, GLRA establishes a formulaic correlation between the transmission cost and the design’s overall risk of information leakage. Experiments on cryptographic cores, debug infrastructure, and non-cryptographic logic demonstrate that GLRA accurately quantifies maximum-risk leakage paths, achieving a 18.75% improvement in detection precision over traditional anomaly-based approaches. GLRA correctly determines the presence or absence of leakage risks across all 16 evaluated benchmarks. Furthermore, it supports comparative analysis of leakage mitigation strategies across diverse hardware designs, providing quantitative insights into the effectiveness of protection mechanisms.

As the complexity of integrated circuit (IC) design increases and its manufacture globalizes, IC designers are increasingly adopting third-party intellectual property (IP) cores to reduce costs and expedite development. However, this shift heightens security risks, particularly the threat of Hardware Trojan (HT). Traditional HT detection methods based on neural network are focused on digital circuits, thus not applicable to analog circuits. To bridge this gap, we introduce GAT-Trans, a Graph Attention Network (GAT) model tailored for detecting analog hardware Trojans, such as A2 Trojan, at the transistor level. Since GAT model enhances weights for critical neighboring nodes, GAT-Trans can improve the detection performance of potential HTs embedded within analog circuits. In the paper, we assess the influence of various node definition methods on detection efficacy and innovate a graph construction method that treats ports of one transistor as a node. We systematically explore different feature extraction methods from analog circuits and evaluate model performance across different feature combinations. This paper details GAT-Trans and proves its effectiveness in identifying A2 Trojan, offering a novel security tool for analog circuits and enhancing defenses against advanced hardware threats.

The globalization of the IC industry has led to hardware designers commonly adopting Third-Party Intellectual Property cores (3PIPs) to reduce design costs and time. However, over-reliance on untrustworthy 3PIPs may compromise the autonomy of ICs and provide opportunities for the Hardware Trojans (HT) implantation, thus reducing the security and trustworthiness of hardware designs. Existing methods of artificial intelligence have drawbacks of dependence on a golden HT-free model, low accuracy, and long detection time when identifying and detecting HTs in large-scale gate-level netlists (GLNs). To enhance the accuracy of HT detection in IP cores and reduce detection time, we propose a novel HT detection method using the controllability metric and the Gated Recurrent Unit (GRU) neural network to extract circuit sequence features and detect HTs. With the advantages of narrowing down the circuit detection range by the controllability metric and the simplicity and efficiency of the GRU neural network, our method achieves an average TPR detection accuracy of 95.5% and an average TNR detection accuracy of 99.6%. Compared with other existing methods, our method has high detection accuracy and effectively reduces the detection time.

The presence of always-on hardware Trojans (HTs) capable of continuously leaking sensitive information poses a significant threat to security, particularly in circuits designed for sensitive information protection. These HTs are engineered to operate stealthily, making their detection a formidable challenge. While existing hardware Trojan detection methodologies often rely on the identification of rare triggering characteristics, they prove inadequate for effectively identifying always-on HTs. This paper presents a novel approach to detect such HTs, which persistently leak critical information within circuits designed for sensitive information protection. By analyzing the characteristics of always-on information-leakage HTs, we propose CA4TJ, a corresponding quantifying metric to evaluate the correlation between sensitive information and the leaked port within gate-level netlists. Distinguished from conventional methods, the proposed approach eliminates the need for a reference model, thereby enhancing its practicality in real-world applications. The efficacy of this method is validated through extensive evaluations conducted on benchmark circuits, including those with intricate designs comprising up to one hundred thousand gates.

Hardware Trojans (HTs) pose a significant and growing threat to the field of hardware security. Several side-channel techniques, including power and electromagnetic radiation (EMR), have been proposed for HT detection, constrained by reliance on the golden chip or test vectors. In response, researchers advocate for the use of thermal radiation (TR) to identify HTs. However, existing TR-based methods are designed for the ideal HT that can fully occupy at least one pixel on the thermal radiation map (TRM). In reality, HTs may occupy multiple pixels, substantially diminishing occupancy in each pixel, thereby reducing the accuracy of existing detection methods. This challenge is exacerbated by the noise caused by the thermal camera. To this end, this paper introduces a countermeasure named noise based pixel occupation enhancement (NICE), aiming to improve the ability of TR-based HT detection. The key insight of NICE is that noise can vary the pixel occupation of HTs while disrupting HT detection. Consequently, the noise can be exploited to statistically find out the largest pixel occupation among the variations, thereby enhancing HT detection accuracy. Experimental results on a 0.13 mu m Digital Signal Processing (DSP) show that the detection rate of NICE exceeds the existing TR-based method by more than 47%, reaching 91.81%, while maintaining a false alarm rate of less than 9%. Both metrics of NICE are comparable to the existing power-based and EMR-based methods, eliminating the need for the golden chip and test vectors.

Physical Unclonable Function(PUF)-based security protocols are effective in mitigating various security threats, including eavesdropping, interception, and cloning. Nevertheless, most existing protocols are implemented in software, with the primary drawback being their inability to integrate with actual PUF and their inefficiency. Although some strategies incorporate PUF into their design, these systems do not allow for configuration changes and are deficient in flexibility. In this paper, we propose the CoDPoC IP, a configurable data protection circuit that supports PUF-based various key agreement authentication schemes and allows for flexible scheme design adjustments through configurable registers. The CoDPoC IP offers two advantages: 1) hardwarelevel implementation incorporates PUF, leading to higher resource utilization, efficiency, and security; and 2) the IP supports flexible configuration of schemes. Experimental results indicate that the hardware execution time is 0.03504 milliseconds. The proposed scheme is successfully implemented and verified with low-overhead hardware.

In the context of the globalization of the Integrated Circuit (IC) industry, the Intellectual Property Cores (IPs) assume a pivotal role, offering the potential to streamline the development process and reduce costs. However, the use of IPs from third parties introduces the potential for malicious modifications, such as the insertion of hardware Trojans (HTs), which can compromise the security and reliability of hardware designs. Despite the advent of deep learning-based HT detection methods that leverage circuit sequences and graph data, which have overcome the limitations of a lack of a golden model and scalability issues, there are still shortcomings in the utilization of global and local features. We develop an HT detection method SFCM-HT based on a combination model of the graph convolutional network (GCN) and the gated recurrent unit (GRU). We transform the Register Transfer Level (RTL) design to a graph structure and model the graph as fixed-length sequences and innovatively construct the combination model to predict sequences related to HTs. We exploit the capacity of GCN to learn features locally and utilize circuit structure information globally, as well as the aptitude of GRU for learning and predicting circuit sequence features. We evaluate the model based on benchmark circuits in Trusthub. SFCM-HT detects Trojan sequences with 98.20% Precision and 98.76% Recall and effectively reduces detection time.

The static random-access memory (SRAM) physical unclonable function (PUF) uses the power-up states of stored values to derive the identification code. Its lightweight circuit design makes it suitable for power-sensitive satellites. However, the SRAM PUF is significantly affected by high-energy particles and cosmic rays in space, which causes incorrect output of identity authentication codes and further leading to a degradation in reliability. Recently, the main research works are concerned about the impact of cosmic rays induced total ionizing dose effects on the SRAM PUF, and few reports discuss the high-energy particles induced single event effects on the SRAM PUF. This paper presents the reliability results of planar and FinFET-based SRAM PUFs after high-energy heavy ion experiments. Experimental results indicate that 3%–10% of the SRAM PUF bits change from their original power-on states, which demonstrate that ion-induced microdose effects degrade the reliability of SRAM PUFs. In addition, the three-dimensional technology computer-aided design simulation tool is used to analyze the physical mechanisms of the experimental phenomena. Simulation results show that the heavy ion-induced microdose effect ionizes and produces trapped charges at the silicon/insulation interface, which causes a slight change in transistor leakage current or a slight drift in threshold voltage. The physical mechanisms lead to an off-state current mismatch in the SRAM cell and finally affect the stored values after power-on.

The remarkable advance of the Internet of Things (IoT) has smoothed the way to the interconnection of various mobile devices in secure access and communication. In order to guarantee user privacy and anonymity in public networks, a large number of mutual authentication and key-sharing protocols between different IoT devices and multi-servers have been proposed. Due to resource-constrained and inefficient IoT devices, most previous protocols can confront assorted malicious attacks, such as eavesdropping, counterfeiting, chip cloning, device forgery, and other attacks. These attacks may be exposed the user’s private key or other sensitive data. To solve these problems, physical unclonable function (PUF) is a lightweight security primitive that utilizes random process deviations that cannot be controlled during chip manufacturing to generate device-unique digital signatures. In this paper, we combined the key-sharing scheme based on PUF on the hardware side, which solves relevant security problems such as device cloning and key tampering. Furthermore, we propose a three-factor secure and efficient authentication and key-sharing protocol, leveraging the inherent security properties of passwords, biometrics, and PUFs. We demonstrate the security of our proposed protocol based on computational Bilinear Diffie–Hellman Problem (BDH) and k-CAA hard problems and the Proverif tool. Compared with existing relevant protocols, our protocol meets various security properties and defends against varied security threats. The low computational cost, communication overhead, and device storage indicate that our protocol is applicable to resource-constrained IoT devices.

Aiming at the problem that complex security primitives in existing schemes were not suitable for resource-constrained IoT devices, a lightweight efficient anonymous identity authentication protocol for IoT devices was designed based on physical unclonable function (PUF).Through the formal security model and ProVerif tool, it was proved that the protocol satisfies 13 security properties such as information confidentiality, integrity, un-traceability, and forward/backward secrecy.Compared with existing relevant protocols, the computing overhead of the protocol on the device side and the server side is 0.468 ms and 0.072 ms respectively, and the device storage and communication overheads are 256 bit and 896 bit respectively, which is highly suitable for lightweight IoT devices with limited resources.

The remarkable growth of the Internet of Things (IoT) has paved the way for the interconnection of a wide variety of mobile devices. To protect data confidentiality and user privacy in public networks, most key sharing and management protocols have gained wide attention. Due to the limited resources of IoT devices, relevant security primitives with high communication overhead and slow transmission rates are not suitable for the authentication of lightweight devices. To solve these problems, physical unclonable function (PUF) is lightweight security primitive that exploits the frequency difference during the chip fabrication process for the key generation or device authentication. In this paper, we flexibly configure the oscillation period of the reconfigurable HCRO-PUF to generate a shared key on the hardware side, which solve related security problems such as device cloning and key tampering. Furthermore, we propose a lightweight key sharing and management (LKSM) protocol based on HCRO-PUF for various devices and multi-server architectures. We prove that the proposed protocol satisfies the corresponding security and resistance properties through Ban logic. Compared with existing relevant protocols, security analysis and simulation results show that our protocol defends against multiple attacks. The low computational and communication costs indicate that our protocol is suitable for resource-constrained IoT devices.

In the era of big data, information security is faced with many threats, among which memory data security of intelligent devices is an important link. Attackers can read the memory of specific devices, and then steal secrets, alter data, affect the operation of intelligent devices, and bring security threats. Data security is usually protected by encryption algorithm for device ciphertext conversion, so the safe generation and use of key becomes particularly important. In this paper, based on the advantages of SRAM PUF, such as real-time generation, power failure and disappearance, safety and reliability, a key generation unit is designed and implemented. BCH code is used as the error correction algorithm to generate 128-bit stable key, which provides a guarantee for the safe storage of intelligent devices.

Side-channel attacks are one of the security threats to the chip-level devices of the communication systems. To strengthen chip-level cryptographic devices against side-channel attacks, a current equalizer that weakens the current difference is proposed, which barely changes the original design flow and is resistant to physical teardown. This method overlays (metal-insulator-metal) MIM capacitors on top of the critical modules in chip-level components, thus weakening the differences in supply current at different inputs. Meanwhile, the proposed countermeasure is an anti-physical teardown, due to the way the MIM capacitors are connected longitudinally to the power network of the key modules. Experimental results show that this approach is highly resistant to DPA, which has the lowest security evaluation metrics value and area overhead than three existing DPA countermeasures.

With the globalization of the integrated circuit industry, hardware Trojan is becoming the main threat to integrated circuits. At present, the side-channel analysis which can make a good trade-off between detection ability and cost, has attracted more attention from the academia. The side-channel analysis method based on electromagnetic radiation is one of the hotspots in hardware security field. The ability evaluation of electromagnetic radiation analysis method to detect hardware Trojan was focused, and the factor that limited their detection performance was explored. The experimental results on FPGA show that the electromagnetic radiation analysis method can effectively detect hardware Trojan whose electromagnetic radiation distribution is significantly different from surrounding circuits, but it cannot be applied to hardware Trojan with complex frequency distribution of electromagnetic radiation.

Hardware Trojan is increasingly becoming a major threat in the filed of hardware security. To solve that security threat, we propose a novel strategy for hardware Trojan detection combining trustworthy design with thermal radiation analysis. We use ring oscillators to fill the vulnerable area of target IC, and their layouts can serve as the trustworthy reference. Ring oscillator's thermal radiation is related to its stage, so that the location and stage of ring oscillators can be extracted from thermal maps by k-means clustering. Removing, breaking or degrading ring oscillators to insert a hardware Trojan can be detected by thermal radiation analysis. Therefore, our countermeasure can efficiently and conveniently detect the insertion of hardware Trojan without fabricated golden-chip. Experimental results on FPGA show that our countermeasure can accurately identify the thermal radiation change of ring oscillators and be used for hardware Trojan detection.

Physical unclonable function (PUF), a reliable and lightweight physical security primitive for secret key generation and anti-tampering. Strong PUF is an important PUF classification that provides a large "Challenge-Response" pairs (CRP) space for device authentication. However, none of the existing PUF constructions is both machine learning (ML) attack resistant and sufficiently lightweight to fit the low-end internet of things and embedded devices. A lightweight composition PUF design, Shift Register based PUF (SRPUF), is proposed in which the time delay performance is sacrificed to make the PUF structure variable and difficult to derive a stable model. A linear feedback shift register (LFSR) is used to de-synchronized the input challenges and output responses of the SRPUF. The LFSR can be configured dynamically to provide a high entropy source and large enough CRP space. The SRPUF is simulated in Python then implemented on a 28 nm FPGA. The experimental results show that the uniformity and uniqueness of the PUF is 49.8%, 49.9%, which is close to the ideal value, and the hardware overhead is small. Meanwhile, it shows excellent resistance to several popular ML attack methods. This new PUF design idea is suitable for resource-constrained and time delay-insensitive applications.

Hardware Trojan (HT) is increasingly becoming a major threat in the filed of hardware security. Recently, researchers are taking a high value on the side-channel countermeasures. Meanwhile, the electromagnetic radiation (EMR) based method is one of the most promising schemes to ensure whether integrated circuit (IC) is HT-infected or not. In this paper, we focus on the ability evaluation for existing EMR based methods to implement the HT detection. We propose the noise model based on analyses of noise sources during HT detection using EMR. Then, we study the effect caused by several types of noises in this model. According to these analyses, we discuss the limitation for EMR based methods in two special scenarios, and propose an evaluation scheme to evaluate the detection capability for using EMR analysis to identify HTs. Finally, we exemplify our scheme with some experiments. Experimental results on FPGA show the effectiveness of EMR based methods as well as their limitations.

差分功耗攻击技术是恢复密码设备密钥最有效的攻击手段之一,但在攻击过程中,如果使用不合适的采样点,将引入额外噪声,会降低攻击成功率.为此,提出了一种基于能量模型的能量迹分类方法,旨在定位能量迹中与密钥具有较强相关性的特征点.分别利用汉明距离和汉明重量2种能量模型定位特征点,截取特征点附近少量采样点构成特征区间.攻击不同密钥下载有128位AES算法的SoC芯片,实测结果表明:利用汉明距离能量模型得到的最佳特征区间的长度较短.最终,基于汉明距离能量模型得到的特征点定位方法具有较低的样本计算量,且缩减了大量的样本量.

The side-channel attacks (SCAs) use the correlation between the power leakage information and the key to implement the attack process. The result of SCAs has a certain probability. If guessing an 8-bit key, there is a probability of 1/256 that the key will be guessed coincidentally, resulting in false positive. Therefore, the reliability of result key also needs an index to measure. Thereby, this paper proposes a novel evaluation index based on confidence value (CV). The CV of result key is divided three levels, low false positive, medium false positive and high false positive. CV provides a new reference index for the designers, suppliers and users of cryptographic devices to evaluate the security of devices.