As an upgraded version of ZUC-128, ZUC-256 serves as a stream cipher algorithm in high-speed communication (e.g. 5G mobile communication) for data confidentiality and integrity protection. However, the multi-input modulo ( 2^31 - 1 ) addition used in its linear feedback shift register forms a performance bottleneck. Existing approaches typically decompose the multi-input modulo ( 2^31 - 1 ) addition into a series of two-input modular addition and insert pipeline registers to shorten critical path delay. Although this method helps to raise the throughputs, it significantly increases register cost. To address this issue, an area-efficiency Compression Array Modulo ( 2^31 - 1 ) Adder (CAMA) is proposed. The CAMA can achieve high speed comparable to the traditional two-input modulo ( 2^31 - 1 ) adder without requiring additional pipeline registers. Moreover, by combining bit-width partitioning with parallel addition optimization, the 31-bit carry chain in the CAMA can be reduced to 16 bits. Furthermore, we apply the bit-width partitioning strategy to the finite state machine module of ZUC-256, effectively balancing delays across pipeline stages. To evaluate the performance of our proposal, we conduct experiments on three platforms including Spartan-6, Virtex-5, and Virtex-7 FPGA. On the Spartan-6 platform, the proposed design achieves a maximum throughput of 4103 Mbps, improving 18.0

To address the information leak problem in cloud computing, privacy protection techniques are receiving widespread attention. Among them, the Paillier homomorphism algorithm is an effective one since it allows addition and scalar multiplication operations when information is in decrypted state. However, its computational efficiency is limited by complex modulo operations due to the ciphertext expansion followed by encryption. To accelerate its decryption, the Chinese Remainder Theorem (CRT) is often used to optimize these modulo operations, which makes the decryption chain undesirably long in turn. To address this issue, we propose an eCRT-Paillier decryption algorithm that shortens the decryption computation chain by combining precomputed parameters and eliminating extra judgment operations introduced by Montgomery modular multiplications. These two improvements reduce 50% modular multiplications and 60% judgment operations in the postprocessing of the CRT-Paillier decryption algorithm. Based on these improvements, we propose a highly parallel full-pipeline architecture to remove stalls caused by multiplier reuse in traditional modular exponentiation operations. This architecture also adopts some optimization methods, such as simplifying modular exponentiation units by dividing the exponent into segments and parallelizing data flow by multi-core instantiation. Finally, a high-throughput and efficient Paillier accelerator named MESA is implemented on the Xilinx Virtex-7 FPGA for evaluation. As the experimental result shows, it can complete a decryption within 0.577ms under a 100 MHz clock when using a 2048-bit key. Compared with previous works in the identical conditions, MESA can achieve a 1.16 × to 313.21 × increase in throughput, as well as 2.59% to 96.04% improvement in the Area Time Product (ATP).

With the widespread deployment of neural networks on edge devices, model parameters have become valuable intellectual property and are increasingly threatened by model cloning and unauthorized use. To address this issue, we propose a neural network model protection method based on hardware binding and selective encryption. First, a device-unique key is dynamically generated from a PUF to bind the model to a specific hardware instance. Then, a selective parameter encryption strategy based on channel-level importance and layer-wise weighting is introduced to prioritize critical weights under a limited encryption ratio, thereby reducing the performance overhead of weight protection. Finally, selected model parameters are protected using the ChaCha20 stream cipher, enabling protection against model cloning and theft. Experimental results on image classification, speech recognition, and text recognition tasks show that the proposed method can significantly reduce inference accuracy on unauthorized devices at low encryption ratios, while maintaining performance close to the original model on authorized devices. Compared with random encryption, the proposed scheme requires fewer encrypted parameters under the same security level, thereby providing a favorable trade-off between security and efficiency.

Modular inversion is a computational bottleneck in Elliptic Curve Cryptography (ECC) over prime fields. In affine coordinate implementations, both point addition and point doubling rely on modular inversion, while projective coordinates, such as Jacobian coordinates, reduce inversion frequency at the cost of additional multiplications. Nevertheless, modular inversion remains a key factor determining performance and resource overhead, especially in high-performance and resource-constrained scenarios. To address these issues, this paper proposes an efficient radix-4 modular inversion algorithm for odd moduli and a scalable DSP-based hardware architecture. The method employs low-bit-driven iteration, lightweight constant correction, and segmented parallel computation to reduce control complexity and storage overhead while ensuring correctness. The hardware design utilizes a segmented DSP adder array supporting addition, subtraction, and conditional swapping, achieving high resource utilization and low latency. FPGA implementation results demonstrate a 2–3× increase in frequency, an approximately 40% reduction in latency, and 50%–65% savings in LUT/FF resources, outperforming existing approaches in area-time efficiency.

After being selected as a standard for Post-Quantum Cryptography Key Encapsulation Mechanisms by NIST, CRYSTALS-Kyber has driven the transformation of the information security field toward new standards. In CRYSTALS-Kyber, modular reduction is crucial for performance optimization. This paper proposes a bitwise modular reduction design based on Dadda tree compression arrays, achieving higher parallelism through a strategy that combines bitwise modular reduction with hybrid compression arrays. As our experiments show, it only costs 91 LUTs when implemented on Xilinx Artix-7 FPGA. Compared with the leading hardware implementations, the Area–Time Product (ATP) is reduced by 16.43%~87.69%.

Large-integer modular multiplication (LMM) is a core operation in public-key algorithms, which serve as critical safeguards for information security. Although much effort has been made to improve its efficiency, traditional FPGA-based implementations of LMM still suffer from high complexity, data dependencies, and long latency. To address these issues, this paper proposes an optimized method based on the conventional CIOS (Coarsely Integrated Operand Scanning) modular multiplication algorithm. This proposal eliminates the data dependency between the quotient and the partial product by strategically shifting one operand of LMM. Besides, through asymmetric partitioning of internal operands, our proposal can efficiently exploit the computing power of FPGA by making full use of the embedded asymmetric multipliers, which are not suitable for traditional methods. Experimental evaluations on two widely adopted FPGA platforms demonstrate significant advantages of our proposal in both latency and area efficiency compared to state-of-the-art implementations. Our fastest version can achieve latencies of 0.52µs and 0.26µs for 2048-bit LMM and 1024-bit LMM, respectively, which saves 17% and 21% over the state-of-the-art implementation.

With the rapid development of Artificial Intelligence & Internet of Things (AIoT), billions of intelligent devices are connected together, enabling smart control and convenient access. However, this interconnectedness also poses a serious risk of privacy breaches and malicious hijacking. As an emerging hardware security primitive, physical unclonable function (PUF) can be used for lightweight authentication. Yet, its vulnerability to modeling attacks necessitates complex design, leading to high costs and low reliability. To tackle this issue, this paper leverages the existing hardware in AIoT devices and proposes a neural networkbased PUF (NN-PUF) protection method to obfuscate PUF responses, effectively enhancing PUF resilience against modeling attacks. Experimental results demonstrate that with a single-layer binary fully connected network of only 8 neurons, the PUF utilizing 16-bit responses remains secure even when the number of training data increases to 5.12 million, validating the effectiveness of our method against modeling attacks. Furthermore, due to the inherent fault tolerance of neural networks, our approach does not compromise reliability as much as traditional methods.

Physical unclonable functions (PUFs) provide a promising solution for enhancing security and device authentication. Strong PUFs can generate quantities of challenge-response pairs(CRPs) but are vulnerable to machine learning (ML) attacks. Weak PUFs must restrict direct access to the original response because they have limited CRPs. In this article, we present a Shuffled Chaotic-dual-PUF structure(SCD-PUF) to defeat against ML attacks. Its working procedure is divided into two main stages: In the first phase, the weak PUF is used to generate secret bits as parameters for the chaotic configuration and along with the secret bits generated by the chaotic process, serve as the obfuscation configuration for the second phase. The second stage involves the Knuth-Durstenfeld shuffle algorithm, concatenation and XOR operations to obfuscate the challenges and responses at the same time. To prove the effectiveness of our proposal, we implement an example of SCD-PUF using Static Random-Access Memory(SRAM) PUF and Arbiter PUF(APUF) on Xilinx ZedBoard FPGAs. Using Logistic Regression (LR), Support Vector Machine (SVM), and Artificial Neural Networks (ANN) as attacking methods, the learning accuracy is maintained at around 51% even when the training data increase to one million, which proves our proposal has enough resistance to ML attacks. Also, the area overhead of our proposal is appropriate and acceptable.

Physical Unclonable Function(PUF)-based security protocols are effective in mitigating various security threats, including eavesdropping, interception, and cloning. Nevertheless, most existing protocols are implemented in software, with the primary drawback being their inability to integrate with actual PUF and their inefficiency. Although some strategies incorporate PUF into their design, these systems do not allow for configuration changes and are deficient in flexibility. In this paper, we propose the CoDPoC IP, a configurable data protection circuit that supports PUF-based various key agreement authentication schemes and allows for flexible scheme design adjustments through configurable registers. The CoDPoC IP offers two advantages: 1) hardwarelevel implementation incorporates PUF, leading to higher resource utilization, efficiency, and security; and 2) the IP supports flexible configuration of schemes. Experimental results indicate that the hardware execution time is 0.03504 milliseconds. The proposed scheme is successfully implemented and verified with low-overhead hardware.

As new lightweight hardware security primitive, the physical unclonable function (PUF) is used in various hardware-based secure applications like keys generation and device authentication. But PUFs are vulnerable to modeling attacks using machine learning (ML) technology. To solve the problem, a dynamically configurable obfuscation unit for PUF using a dynamic linear feedback shift register (DLFSR) is proposed. The structure of this obfuscation unit can change with the clock cycle running, making the PUF difficult to model. Using the obfuscation unit, a dual-PUF-based mutual device authentication protocol for low-cost IoT systems is proposed. New technologies like dual-stage and device-to-server authentication are used to limit the amount of data that an attacker can obtain. A random pattern-based mechanism is introduced to the protocol to enhance the robustness against physical attacks. A mathematical model of the proposed unit is presented and analyzed. Experimental results on FPGA show that the design is simpler, more reliable, and lightweight. It can effectively resist ML-based attacks and physical attacks.

The remarkable advance of the Internet of Things (IoT) has smoothed the way to the interconnection of various mobile devices in secure access and communication. In order to guarantee user privacy and anonymity in public networks, a large number of mutual authentication and key-sharing protocols between different IoT devices and multi-servers have been proposed. Due to resource-constrained and inefficient IoT devices, most previous protocols can confront assorted malicious attacks, such as eavesdropping, counterfeiting, chip cloning, device forgery, and other attacks. These attacks may be exposed the user’s private key or other sensitive data. To solve these problems, physical unclonable function (PUF) is a lightweight security primitive that utilizes random process deviations that cannot be controlled during chip manufacturing to generate device-unique digital signatures. In this paper, we combined the key-sharing scheme based on PUF on the hardware side, which solves relevant security problems such as device cloning and key tampering. Furthermore, we propose a three-factor secure and efficient authentication and key-sharing protocol, leveraging the inherent security properties of passwords, biometrics, and PUFs. We demonstrate the security of our proposed protocol based on computational Bilinear Diffie–Hellman Problem (BDH) and k-CAA hard problems and the Proverif tool. Compared with existing relevant protocols, our protocol meets various security properties and defends against varied security threats. The low computational cost, communication overhead, and device storage indicate that our protocol is applicable to resource-constrained IoT devices.

Aiming at the problem that complex security primitives in existing schemes were not suitable for resource-constrained IoT devices, a lightweight efficient anonymous identity authentication protocol for IoT devices was designed based on physical unclonable function (PUF).Through the formal security model and ProVerif tool, it was proved that the protocol satisfies 13 security properties such as information confidentiality, integrity, un-traceability, and forward/backward secrecy.Compared with existing relevant protocols, the computing overhead of the protocol on the device side and the server side is 0.468 ms and 0.072 ms respectively, and the device storage and communication overheads are 256 bit and 896 bit respectively, which is highly suitable for lightweight IoT devices with limited resources.

With the separation of design and manufacture in semiconductor industry, self-designed circuits are exposed to hardware Trojan attacks when they are outsourced to an untrustworthy foundry. Trojans activated by digital logic have gained extensive attention. However, those with analog trigger component remain as a serious issue such as the A2 Trojan. Existing defense against A2 Trojans mainly relies on runtime detection mechanism which needs large monitor hardware overhead and complicated identification/handling software. To address these limitations, this article proposes a built-in structure to accelerate the activation of A2 Trojans, which consists of several composite-logic ring oscillators and a multiple-purpose controller. In addition, two post-fabrication detection schemes named time-division mode-switching (TDMS) and scan-based fault test compatible (SFTC) are proposed. TDMS detection scheme can discover A2 Trojans when running functional patterns by inserting oscillating operations every other cycle. SFTC detection scheme can detect A2 Trojans during scan-based fault test by introducing oscillation before each capture operation. Evaluations across a wide range of A2 Trojans and benchmarks show that our proposal is more power-efficient and area-saving compared with existing monitor structure.

Physical unclonable function (PUF), a reliable and lightweight physical security primitive for secret key generation and anti-tampering. Strong PUF is an important PUF classification that provides a large "Challenge-Response" pairs (CRP) space for device authentication. However, none of the existing PUF constructions is both machine learning (ML) attack resistant and sufficiently lightweight to fit the low-end internet of things and embedded devices. A lightweight composition PUF design, Shift Register based PUF (SRPUF), is proposed in which the time delay performance is sacrificed to make the PUF structure variable and difficult to derive a stable model. A linear feedback shift register (LFSR) is used to de-synchronized the input challenges and output responses of the SRPUF. The LFSR can be configured dynamically to provide a high entropy source and large enough CRP space. The SRPUF is simulated in Python then implemented on a 28 nm FPGA. The experimental results show that the uniformity and uniqueness of the PUF is 49.8%, 49.9%, which is close to the ideal value, and the hardware overhead is small. Meanwhile, it shows excellent resistance to several popular ML attack methods. This new PUF design idea is suitable for resource-constrained and time delay-insensitive applications.

由宇宙辐射等环境因素引起的硬件瞬时故障会极大降低计算机系统的可靠性.为了减小硬件瞬时故障对系统可靠性的影响,保证程序的正确运行,基于RISC-V开源内核"蜂鸟e203"提出一种标记指令复算与纠错机制.该机制为指令码额外增加了复算标记,以较小的硬件开销实现对指定指令的复算操作.此外,该机制可以在第一次复算结果与初始运算结果不等时自动进行二次复算,并由三次运算结果的多数表决结果来纠正大部分硬件瞬时故障所引起的数据流异常.实验表明,通过与中断处理程序相结合,在随机注入瞬时故障的情况下,程序的正确执行概率平均增加了86.67％.

Physical unclonable function (PUF), a hardware that can extract the differences of the same implementations and provide unique secret keys without the utilization of non-volatile memory, is regarded as a promising security primitive in the near future. Ring Oscillator (RO) PUF is one of its easy silicon implementations, which exploits the frequency difference between a pair of structurally identical ring oscillators. However, a large number of ROs must be constructed if multiple stable output bits are required, which means unacceptable area overhead for lightweight applications. To solve this problem, configurable ROs using multiplexers and different delay units were proposed in previous papers. Unfortunately, most of them take advantage of the specific structure of a certain type of field-programmable gate arrays (FPGAs), thus not cost-saving for application-specific integrated circuit (ASIC). In this paper, we propose a configurable RO using only two hybrid logic gates in each stage for ASIC, which costs less area and power compared with previous proposals. Experiment on 50 FPGAs and one self-designed printed circuit board demonstrates satisfactory uniformity and uniqueness of this novel RO PUF. Furthermore, our proposal is proved to be reliable in a wide variety of environment conditions.

Physical unclonable function (PUF) is a reliable physical security primitive. The Weak PUF and Strong PUF are two well-known PUF topologies. Strong PUF can be used to authenticate and protect intellectual property on FPGA chips. Classic PUF designs, like arbiter PUF, are hard to implement on FPGA and severely threatened by the machine learning based modeling attacks. In this work, we propose a new Strong PUF on FPGA by combining Weak PUF with obfuscation logic. Experiment results on a 28nm FPGA show that the resistance to modeling attack is good and the hardware overhead is small.

As the serial scan design has been one of the most popular methods in VLSI circuit test, power consumption during test increases significantly because of its inherent shift mode. To solve this problem, this paper proposes a novel test scheme, which makes a few improvements in the traditional scan architecture and adopts a new two-phase approach. First, each clock chain is activated in turn and the vectors for scan cells in the activated chain are applied in parallel within a test clock period. Second, after one pattern has been applied completely, all chains are activated to capture the response altogether. In addition, a compression algorithm is proposed to augment the parallelism of our method. Experimental results on benchmark circuits and industrial modules show that, compared with the traditional serial scan scheme, the proposed approach can reduce average power by 88.98% and peak power by 59.99% at acceptable area and wire length cost.

A novel power-efficient IC test scheme is proposed, containing parallel test application (PTA) architecture and its procedure. PTA parallelizes the stimuli assignments and the vectors can be observed immediately once applied, which assures the shift safety timely and hence only logic test is required. The procedure contains two phases for each pattern. In shift phase, each clock chain is activated in turn and the vectors are assigned in parallel. In capture phase, all chains are captured simultaneously. Experimental results demonstrate that, compared with the traditional serial scan scheme, the proposal reduces average power by 88.48% and peak power by 53.36%.